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MC14557B データシートの表示(PDF) - ON Semiconductor

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MC14557B Datasheet PDF : 8 Pages
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MC14557B
ÎÎÎÎSWÎÎITCÎÎHINÎÎG CÎÎHARÎÎACÎÎTERÎÎISTÎÎICSÎÎ(NoÎÎte 6ÎÎ) (CLÎÎ= 5ÎÎ0 pFÎÎ, TAÎÎ= 25ÎΰC) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTypÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Characteristic
VDD
Min
(Note 7)
Max
Unit
tTLH,
tTHL
Rise and Fall Time, Q or Q Output
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
ns
5
100
200
10
50
100
15
40
80
tPLH,
tPHL
Propagation Delay, Clock or CE to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
ns
5
300
600
10
130
260
15
90
180
tPLH,
tPHL
Propagation Delay, Reset to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns
ns
5
300
600
10
130
260
15
95
190
tWH(cl)
Pulse Width, Clock
5
200
95
10
100
45
ns
15
75
35
tWH(rst)
Pulse Width, Reset
5
300
150
10
140
70
15
100
50
ns
fcl
Clock Frequency (50% Duty Cycle)
5
3.0
1.7
MHz
10
7.5
5.0
15
13.0
6.7
tsu
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
5
700
350
10
290
130
15
145
85
ns
Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
400
45
10
165
5
15
60
0
th
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
ns
5
200
–150
10
100
–60
15
10
–50
Worst case condition: L32 = VDD, L1 through L16 =
5
400
50
Don’t Care (Any register length from 33 to 64)
10
185
25
15
85
22
tr,
Rise and Fall Time, Clock
tf
5
10
No Limit
15
tr,
Rise and Fall Time, Reset or CE
tf
5
10
15
15
ms
5
4
trem
Removal Time, Reset to Clock or CE
5
160
80
10
80
40
15
70
35
ns
6. The formulas given are for the typical characteristics only at 25°C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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