MC33661D データシートの表示（PDF） - Freescale Semiconductor

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MC33661D

Local Area Network (LIN) Enhanced Physical Interface with Selectable Slew Rate

Freescale Semiconductor 

TIMING DIAGRAMS

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

TXD

Recessive State

VREC

LIN

t DOM(MIN)

RXD

58.1% VSUP

40% VSUP

t DOM(MAX)

28.4% VSUP

VDOM

Dominant State

t REC(MIN)

t REC(MAX)

74.4% VSUP

60% VSUP

42.2% VSUP

tRL

tRH

Figure 4. Normal Mode Bus Timing Characteristics

TXD

Recessive State

VREC

LIN

t DOM(MIN)

RXD

61.6% VSUP

40% VSUP

t DOM(MAX)

25.1% VSUP

VDOM

Dominant State

t REC(MIN)

t REC(MAX)

77.8% VSUP

60% VSUP

38.9% VSUP

t RL

t RH

Figure 5. Slow Mode Bus Timing Characteristics

VSUP

VSUP

TXD

R0

RXD

LIN

GND

C0

Note R0 and C0: 1.0 kΩ/1.0 nF, 660 Ω/6.8 nF, and 500 Ω/10 nF.

Figure 6. Test Circuit for Timing Measurements

Analog Integrated Circuit Device Data

Freescale Semiconductor

33661

9

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