MC56F8013PB データシートの表示（PDF） - Freescale Semiconductor

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MC56F8013PB

16-bit Digital Signal Controllers

Freescale Semiconductor 

4

JTAG / EOnCE

CHIP

TAP

Controller

TAP

Linking

Module

GPIO

External

JTAG Port

pdb_m[15:0]

pab[20:0]

xdb2_m[15:0]

56800E

Program reads

can be done on

secondary port

of data memory

xab2[23:0]

cdbw[31:0]

pdb_m[23:0]

Program writes

can be done on

primary port of

data memory

cdbr_m[31:0]

Program

Flash

Data /

Program

RAM

secondary data read port

primary data read port

IPBus

Bridge

To Flash

Control Logic

Note:

Note:

NOTE: All Flash reads and writes are routed through

the Flash interface units, which encapsulate the Flash

memories. This is not shown for clarity’s sake.

IPBus

Figure 1-1 System Bus Interfaces

Flash

Interface

Unit

Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished

by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core

and the Flash memories.

The primary data RAM port is 32 bits wide. Other data ports are 16 bits.

56F8013 Technical Data, Rev. 2

8

Freescale Semiconductor

Preliminary

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