MC56F8013PB データシートの表示（PDF） - Freescale Semiconductor

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MC56F8013PB

16-bit Digital Signal Controllers

Freescale Semiconductor 

To/From IPBus Bridge

Architecture Block Diagram

GPIOAn

GPIOBn

GPIOCn

GPIODn

CLKGEN

(ROSC / PLL /

CLKIN)

8

GPIO A

8

GPIO B

6

GPIO C

4

GPIO D

Interrupt

Controller

Low-Voltage Interrupt

POR & LVI

System POR

SIM

RESET / GPIOA7

COP Reset

COP

IPBus

(Continues on Figure 1-3)

Figure 1-2 Peripheral Subsystem

Table 1-1 Bus Signal Names

Name

Function

Program Memory Interface

pab[20:0]

Program memory address bus. Data is returned on pdb_m bus.

pdb_m[15:0] Program data bus for instruction word fetches or read operations.

cdbw[15:0]

Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus

are used for writes to program memory.)

Primary Data Memory Interface Bus

xab1[23:0]

Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written

on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.

cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.

cdbw[31:0]

Primary core data bus for memory writes. Addressed via xab1 bus.

Secondary Data Memory Interface

xab2[23:0]

Secondary data address bus used for the second of two simultaneous accesses. Capable of

addressing only words. Data is returned on xdb2_m.

xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.

1. Byte accesses can only occur in the bottom half of the memory address space. The Most Significant Bit (MSB) of the

address will be forced to 0.

56F8013 Technical Data, Rev. 2

Freescale Semiconductor

9

Preliminary

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