56F8014(2007) データシートの表示（PDF） - Freescale Semiconductor

部品番号

コンポーネント説明

メーカー

56F8014
(Rev.:2007)

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8014 Signal Pins

Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

Type

State During

Reset

Signal Description

GPIOB7

2

Input/

Output Port B GPIO — This GPIO pin can be individually programmed as

Output disabled, an input or output pin.

internal

pull-up

(TXD)

Input/

enabled, Transmit Data — SCI transmit data output or transmit / receive in

Output pin is in input single wire opeation.

mode

(SCL2)

Input/

Output

Serial Clock — This pin serves as the I2C serial clock.

After reset, the default state is GPIOB7. The peripheral functionality

is controlled via the SIM. See Section 6.3.8.

2. This signal is also brought out on the GPIOB0 pin.

RESET

(GPIOA7)

16

Input

Output Reset — This input is a direct hardware reset on the processor.

disabled, When RESET is asserted low, the chip is initialized and placed in the

internal reset state. A Schmitt trigger input is used for noise immunity. The

pull-up internal reset signal will be deasserted synchronous with the internal

enabled, clocks after a fixed number of internal clocks.

pin is in input

Input/Open mode Port A GPIO — This GPIO pin can be individually programmed as

Drain

an input or open drain output pin. Note that RESET functionality is

Output

disabled in this mode and the chip can only be reset via POR, COP

reset, or software reset.

After reset, the default state is RESET.

GPIOB4

19

Input/

Output Port B GPIO — This GPIO pin can be individually programmed as

Output disabled, an input or output pin.

internal

pull-up

(T0)

Input/

enabled, T0 — Timer, Channel 0

Output pin is in input

mode

(CLKO)

Output

Clock Output — This is a buffered clock signal. Using the

SIM_CLKO Select Register (SIM_CLKOSR), this pin can be

programmed as any of the following: disabled (logic 0), CLK_MSTR

(system clock), IPBus clock, or oscillator output. See Section 6.3.7.

After reset, the default state is GPIOB4. The peripheral functionality

is controlled via the SIM. See Section 6.3.8.

Return to Table 2-2

56F8014 Technical Data, Rev. 9

Freescale Semiconductor

19

Preliminary

Share Link: