56F8014(2007) データシートの表示（PDF） - Freescale Semiconductor

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56F8014
(Rev.:2007)

16-bit Digital Signal Controllers

Freescale Semiconductor 

Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

Type

State During

Reset

Signal Description

GPIOB5

3

(T1)

(FAULT3)

TCK

15

(GPIOD2)

TMS

30

(GPIOD3)

TDI

29

(GPIOD0)

Input/

Output

Input/

Output

Output

Output Port B GPIO — This GPIO pin can be individually programmed as

disabled, an input or output pin.

internal

pull-up

enabled, T1 — Timer, Channel 1

pin is in input

mode

FAULT3 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOB5. The peripheral functionality

is controlled via the SIM. See Section 6.3.8.

Input

Input/

Output

Output Test Clock Input — This input pin provides a gated clock to

disabled, synchronize the test logic and shift serial data to the JTAG/EOnCE

internal port. The pin is connected internally to a pull-up resistor. A Schmitt

pull-up trigger input is used for noise immunity.

enabled,

pin is in input Port D GPIO — This GPIO pin can be individually programmed as

mode an input or output pin.

After reset, the default state is TCK.

Input

Input/

Output

Output Test Mode Select Input — This input pin is used to sequence the

disabled, JTAG TAP controller’s state machine. It is sampled on the rising

internal edge of TCK and has an on-chip pull-up resistor.

pull-up

enabled, Port D GPIO — This GPIO pin can be individually programmed as

pin is in input an input or output pin.

mode

After reset, the default state is TMS.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

Input

Input/

Output

Output Test Data Input — This input pin provides a serial input data stream

disabled, to the JTAG/EOnCE port. It is sampled on the rising edge of TCK

internal and has an on-chip pull-up resistor.

pull-up

enabled, Port D GPIO — This GPIO pin can be individually programmed as

pin is in input an input or output pin.

mode

After reset, the default state is TDI.

Return to Table 2-2

56F8014 Technical Data, Rev. 9

20

Freescale Semiconductor

Preliminary

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