56F8037 データシートの表示（PDF） - Freescale Semiconductor
部品番号
コンポーネント説明
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56F8037 Datasheet PDF : 181 Pages
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56F8037/56F8027 Data Sheet Table of Contents
Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 56F8037/56F8027 Features . . . . . . . . . . . 6
1.2 56F8037/56F8027 Description . . . . . . . . . 8
1.3 Award-Winning Development
Environment . . . . . . . . . . . . . . . . . . . 9
1.4 Architecture Block Diagram . . . . . . . . . . . 9
1.5 Product Documentation . . . . . . . . . . . . . 18
1.6 Data Sheet Conventions . . . . . . . . . . . . . 18
Part 2 Signal/Connection Descriptions . . . 19
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 56F8037/56F8027 Signal Pins . . . . . . . . 24
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Operating Modes . . . . . . . . . . . . . . . . . . 41
3.4 Internal Clock Source . . . . . . . . . . . . . . . 42
3.5 Crystal Oscillator. . . . . . . . . . . . . . . . . . . 42
3.6 Ceramic Resonator . . . . . . . . . . . . . . . . . 43
3.7 External Clock Input - Crystal Oscillator
Option. . . . . . . . . . . . . . . . . . . . . . . 43
3.8 Alternate External Clock Input . . . . . . . . 44
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 44
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 Interrupt Vector Table . . . . . . . . . . . . . . . 45
4.3 Program Map . . . . . . . . . . . . . . . . . . . . . 47
4.4 Data Map . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5 EOnCE Memory Map . . . . . . . . . . . . . . . 50
4.6 Peripheral Memory-Mapped Registers . . 51
Part 5 Interrupt Controller (ITCN) . . . . . . . . 68
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 68
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 Functional Description . . . . . . . . . . . . . . 68
5.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . 70
5.5 Operating Modes . . . . . . . . . . . . . . . . . . 71
5.6 Register Descriptions . . . . . . . . . . . . . . . 71
5.7 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Part 6 System Integration Module (SIM) . . . 93
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 93
6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3 Register Descriptions . . . . . . . . . . . . . . . 95
6.4 Clock Generation Overview . . . . . . . . . 124
6.5 Power-Saving Modes . . . . . . . . . . . . . . 124
6.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 129
Part 7 Security Features. . . . . . . . . . . . . . . 129
7.1 Operation with Security Enabled. . . . . . 129
7.2 Flash Access Lock and Unlock Mechanisms130
7.3 Product Analysis. . . . . . . . . . . . . . . . . . 131
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .131
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . 131
8.2 Configuration . . . . . . . . . . . . . . . . . . . . 131
8.3 Reset Values . . . . . . . . . . . . . . . . . . . . 135
Part 9 Joint Test Action Group (JTAG) . . .140
9.1 56F8037/56F8027 Information . . . . . . . 140
Part 10Specifications. . . . . . . . . . . . . . . . . .140
10.1 General Characteristics . . . . . . . . . . . . 140
10.2 DC Electrical Characteristics . . . . . . . . 144
10.3 AC Electrical Characteristics . . . . . . . . 147
10.4 Flash Memory Characteristics . . . . . . . 148
10.5 External Clock Operation Timing . . . . . 148
10.6 Phase Locked Loop Timing . . . . . . . . . 149
10.7 Relaxation Oscillator Timing. . . . . . . . . 149
10.8 Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 151
10.9 Serial Peripheral Interface (SPI) Timing 152
10.10 Quad Timer Timing. . . . . . . . . . . . . . . . 156
10.11 Queued Serial Communication Interface
(QSCI) Timing . . . . . . . . . . . . . . . 158
10.12 Freescale’s Scalable Controller Area
Network (MSCAN) Timing . . . . . . 159
10.13 Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 159
10.14 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 161
10.15 Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 162
10.16 Equivalent Circuit for ADC Inputs . . . . . 163
10.17 Comparator (CMP) Parameters . . . . . . 164
10.18 Digital-to-Analog Converter (DAC)
Parameters . . . . . . . . . . . . . . . . . 164
10.19 Power Consumption . . . . . . . . . . . . . . . 166
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .168
11.1 56F8037/56F8027 Package and
Pin-Out Information . . . . . . . . . . . 168
Part 12Design Considerations . . . . . . . . . .171
12.1 Thermal Design Considerations . . . . . . 171
12.2 Electrical Design Considerations . . . . . 172
Part 13Ordering Information . . . . . . . . . . . .173
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .174
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
5
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