Analog-to-Digital Converter (ADC) Parameters
Table 10-23 ADC Parameters (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Monotonicity
GUARANTEED
ADC internal clock
fADIC
0.5
—
5
MHz
Conversion range
RAD
VREFL
—
VREFH
V
ADC channel power-up time
tADPU
5
6
16
tAIC cycles3
ADC reference circuit power-up time4
tVREF
—
—
25
ms
Conversion time
tADC
—
6
—
tAIC cycles3
Sample time
tADS
—
1
—
tAIC cycles3
Input capacitance
CADI
—
5
—
pF
Input injection current5, per pin
IADI
—
—
3
mA
Input injection current, total
IADIT
—
—
20
mA
VREFH current
IVREFH
—
1.2
3
mA
ADC A current
IADCA
—
25
—
mA
ADC B current
Quiescent current
IADCB
—
25
—
mA
IADCQ
—
0
10
μA
Uncalibrated Gain Error (ideal = 1)
EGAIN
—
+/- .004
+/- .01
—
Uncalibrated Offset Voltage
VOFFSET
—
+/- 27
+/- 40
mV
Calibrated Absolute Error6
AECAL
—
See Figure 10-22
—
LSBs
Calibration Factor 17
CF1
—
0.002289
—
—
Calibration Factor 27
CF2
—
-25.6
—
—
Crosstalk between channels
—
—
-60
—
dB
Common Mode Voltage
Vcommon
—
(VREFH - VREFLO) / 2
—
V
Signal-to-noise ratio
SNR
—
64.6
—
db
Signal-to-noise plus distortion ratio
SINAD
—
59.1
—
db
Total Harmonic Distortion
THD
—
60.6
—
db
Spurious Free Dynamic Range
SFDR
—
61.1
—
db
Effective Number Of Bits8
ENOB
—
9.6
—
Bits
1. INL measured from Vin = .1VREFH to Vin = .9VREFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1μF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
56F8365 Technical Data, Rev. 7
Freescale Semiconductor
161
Preliminary