MC68CK338 データシートの表示（PDF） - Freescale Semiconductor

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MC68CK338

32-Bit Modular Microcontroller

Freescale Semiconductor 

Freescale Semiconductor, Inc.

Table 6 MCU Signal Function (Continued)

Signal Name

Data Strobe

Data and Size

Acknowledge

Development Serial

In, Out, Clock

Function Codes

Freeze

Halt

Instruction Pipeline

Interrupt Request

Level

Master In Slave Out

Clock Mode Select

Master Out Slave In

Port C

Peripheral Chip

Select

Port E

Port F

Port QS

Quotient Out

Reset

Read-Modify-Write

Cycle

Read/Write

SCI Receive Data

QSPI Serial Clock

Size

Slave Select

Three-State Control

SCI Transmit Data

External Filter

Capacitor

Mnemonic

DS

DSACK[1:0]

DSI, DSO,

DSCLK

FC[2:0]

FREEZE

HALT

IFETCH, IPIPE

IRQ[7:1]

MISO

MODCLK

MOSI

PC[6:0]

PCS[3:0]

PE[7:0]

PF[7:0]

PQS[7:0]

QUOT

RESET

RMC

R/W

RXD

SCK

SIZ[1:0]

SS

TSC

TXD

XFC

Function

Indicates that an external device should place valid data on the data bus

during a read cycle and that valid data has been placed on the bus by

the CPU during a write cycle

Acknowledges to the SIML that data has been received for a write cycle,

or that data is valid on the data bus for a read cycle

Serial I/O and clock for background debugging mode

Identify processor state and current address space

Indicates that the CPU has entered background mode

Suspend external bus activity

Indicate instruction pipeline activity

Request interrupt service from the CPU

Serial input to QSPI in master mode;

serial output from QSPI in slave mode

Selects system clock source

Serial output from QSPI in master mode;

serial input to QSPI in slave mode

SIML digital output signals

QSPI peripheral chip selects

SIML digital input or output port signals

SIML digital input or output port signals

QSM digital I/O port signals

Provides the quotient bit of the polynomial divider

System reset

Indicates an indivisible read-modify-write instruction

Indicates the direction of data transfer on the bus

Serial input to the SCI

Clock output from QSPI in master mode;

clock input to QSPI in slave mode

Indicates the number of bytes to be transferred during a bus cycle

Causes serial transmission when QSPI is in slave mode.

Causes mode fault in master mode

Places all output drivers in a high-impedance state

Serial output from the SCI

Connection for external phase-locked loop filter capacitor

MC68CK338

MC68CK338TS/D

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