MC74AC377N データシートの表示（PDF） - Motorola => Freescale
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MC74AC377N Datasheet PDF : 6 Pages
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MC74AC377
MC74ACT377
Octal D FlipĆFlop
with Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) input loads
all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-
flop’s Q output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ′ACT377 Has TTL Compatible Inputs
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
CE O0 D0 D1 O1 O2 D2 D3 O3 GND
PIN NAMES
D0–D7
CE
Q0–Q7
CP
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
MODE SELECT-FUNCTION TABLE
Operating Mode
Inputs
CP CE Dn
Load ′1′
LH
Load ′0′
LL
Hold (Do Nothing)
HX
XHX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn
H
L
No Change
No Change
FACT DATA
5-1
OCTAL D
FLIP-FLOP WITH
CLOCK ENABLE
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
O0 O1 O2 O3 O4 O5 O6 O7
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