74HC541 データシートの表示（PDF） - ON Semiconductor
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74HC541 Datasheet PDF : 10 Pages
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MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Condition
VCC *55 to
V
25_C v85_C v125_C Unit
VIH Minimum High−Level Input Voltage
VOUT = 0.1 V
|IOUT| ≤ 20 mA
2.0
1.50
1.50
1.50
V
3.0
2.10
2.10
2.10
4.5
3.15
3.15
3.15
6.0
4.20
4.20
4.20
VIL Maximum Low−Level Input Voltage
VOUT = VCC − 0.1 V
|IOUT| ≤ 20 mA
2.0
0.50
0.50
0.50
V
3.0
0.90
0.90
0.90
4.5
1.35
1.35
1.35
6.0
1.80
1.80
1.80
VOH Minimum High−Level Output Voltage VIN = VIL
|IOUT| ≤ 20 mA
2.0
1.9
4.5
4.4
6.0
5.9
1.9
1.9
V
4.4
4.4
5.9
5.9
VIN = VIL
|IOUT| ≤ 3.6 mA 3.0
|IOUT| ≤ 6.0 mA 4.5
|IOUT| ≤ 7.8 mA 6.0
2.48
3.98
5.48
2.34
2.20
3.84
3.70
5.34
5.20
VOL Maximum Low−Level Output Voltage VIN = VIH
|IOUT| ≤ 20 mA
2.0
0.1
4.5
0.1
6.0
0.1
0.1
0.1
V
0.1
0.1
0.1
0.1
VIN = VIH
|IOUT| ≤ 3.6 mA 3.0
|IOUT| ≤ 6.0 mA 4.5
|IOUT| ≤ 7.8 mA 6.0
0.26
0.26
0.26
0.33
0.40
0.33
0.40
0.33
0.40
IIN
Maximum Input Leakage Current
VIN = VCC or GND
6.0
$0.1
$1.0 $1.0
mA
IOZ Maximum 3−State Leakage Current Output in High Impedance State
VIN = VIL or VIH
VOUT = VCC or GND
6.0
$0.5
$5.0 $10.0 mA
ICC Maximum Quiescent Supply
Current (per Package)
VIN = VCC or GND
IOUT = 0 mA
6.0
4
40
160
mA
8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC *55 to
V
25_C
v85_C v125_C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
2.0
80
3.0
30
4.5
18
6.0
15
100
120
ns
40
55
23
28
20
25
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
110
140
165
ns
3.0
45
60
75
4.5
25
31
38
6.0
21
26
31
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
110
140
165
ns
3.0
45
60
75
4.5
25
31
38
6.0
21
26
31
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
60
75
90
ns
3.0
22
28
34
4.5
12
15
18
6.0
10
13
15
CIN Maximum Input Capacitance
10
10
10
pF
COUT Maximum 3−State Output Capacitance (High Impedance State Output)
15
15
15
pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer) (Note 10)
35
pF
10. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
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