SK100E151 データシートの表示（PDF） - Semtech Corporation
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SK100E151 Datasheet PDF : 5 Pages
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SK10/100E151
HIGH-PER.ORMANCE PRODUCTS
Description
.eatures
6-Bit D Register
The SK10/100E151 offers 6 edge-triggered, high-speed, • 1100 MHz Toggle Frequency
master-slave D-type flip-flops with differential outputs, • Extended 100E VEE Range of –4.2V to –5.5V
designed for use in new high-performance ECL systems. • Differential Outputs
This device is fully compatible with MC10E151 and • Asynchronous Master Reset
MC100E151. The two external clock signals (CLK1, CLK2) • Dual Clocks
are gated through a logical OR operation before use as • Internal 75KΩ Input Pulldown Resistors
clocking control for the flip-flops. Data is clocked into • ESD Protection of >4000V
the flip-flops on the rising edge of either CLK1 or CLK2 • Fully Compatible with MC10/100E151
(or both). When both CLK1 and CLK2 are at a logic • Specified Over Industrial Temperature Range:
LOW, data enters the master and is transferred to the
–40oC to +85oC
slave when either CLK1 or CLK2 (or both) go HIGH.
• Available in 28-Pin PLCC Package
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
Pin Description
.unctional Block Diagram
D0
D1
D2
D3
D4
D5
CLK1
CLK2
MR
D
Q0
R
Q0*
D
Q1
R
Q1*
D
Q2
R
Q2*
D
Q3
R
Q3*
D
Q4
R
Q4*
D
Q5
R
Q5*
Pin
D0–D5
CLK1, CLK2
MR
Q0–Q5
Q0*–Q5*
VCCO
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverting Outputs
Output VCC
D5
26
D4
27
D3
28
VEE
1
D2
2
D1
3
D0
4
PLCC
TOP VIEW
18
Q4*
17
Q4
16
VCC
15
Q3*
14
Q3
13
Q2*
12
Q2
Revision 2/ March 27, 2002
1
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