MC88915T データシートの表示（PDF） - Motorola => Freescale

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MC88915T

Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz Versions

Motorola => Freescale 

MC88915TFN160 (continued)

AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 5.0V ±5%, Load = 50Ω Terminated to VCC/2)

Symbol

Parameter

Min

Max

Unit

Condition

tRISE/FALL

Outputs

tRISE/FALL

2X_Q Output

tPULSE WIDTH

(Q0–Q4, Q5, Q/2)

tPULSE WIDTH

(2X_Q Output)

Rise/Fall Time, All Outputs

1.0

(Between 0.2VCC and 0.8VCC)

Rise/Fall Time

0.5

Output Pulse Width: Q0, Q1, Q2, Q3, Q4,

Q5, Q/2 @ VCC/2

Output Pulse Width:

2X_Q @ VCC

80MHz

100MHz

133MHz

160MHz

0.5tCYCLE – 0.5 2

0.5tCYCLE – 0.7

0.5tCYCLE – 0.5

0.5tCYCLE – 0.5

TBD

2.5

1.6

0.5tCYCLE + 0.5 2

0.5tCYCLE + 0.7

0.5tCYCLE + 0.5

0.5tCYCLE + 0.5

TBD

ns Into a 50Ω Load

Terminated to VCC/2

ns tRISE: 0.8V – 2.0V

tFALL: 2.0V – 0.8V

ns Into a 50Ω Load

Terminated to VCC/2

ns

tPD1

SYNC Feedback

SYNC Input to Feedback Delay

(Measured at SYNC0 or 1 and

FEEDBACK Input Pins)

133MHz

160MHz

(With 1MΩ from RC1 to An VCC)

–1.05

–0.9

–0.25

–0.10

ns See Note 2 and

Figure 2 for Detailed

Explanation

tCYCLE

(2x_Q Output)

Cycle–to–Cycle Variation

133MHz

160MHz

tSKEWr3

Output–to–Output Skew Between Outputs

(Rising) See Note 4 Q0–Q4, Q/2 (Rising Edges Only)

tCYCLE – 300ps

tCYCLE – 300ps

—

tSKEWf3

(Falling)

Output–to–Output Skew Between Outputs

—

Q0–Q4 (Falling Edges Only)

tSKEWall3

Output–to–Output Skew 2X_Q, Q/2,

—

Q0–Q4 Rising, Q5 Falling

tLOCK4

tPZL5

Time Required to Acquire Phase–Lock

1.0

From Time SYNC Input Signal is

Received

Output Enable Time OE/RST to 2X_Q,

3.0

Q0–Q4, Q5, and Q/2

tCYCLE + 300ps

tCYCLE + 300ps

500

500

750

10

ps All Outputs Into a

Matched 50Ω Load

Terminated to VCC/2

ps All Outputs Into a

Matched 50Ω Load

Terminated to VCC/2

ps All Outputs Into a

Matched 50Ω Load

Terminated to VCC/2

ms Also Time to LOCK

Indicator High

14

ns Measured With the

PLL_EN Pin Low

tPHZ,tPLZ5

Output Disable Time OE/RST to 2X_Q,

3.0

Q0–Q4, Q5, and Q/2

14

ns Measured With the

PLL_EN Pin Low

1. TCYCLE in this spec is 1/Frequency at which the particular output is running.

2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.

3. Under equally loaded conditions and at a fixed temperature and voltage.

4. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is with

C1 = 0.01µF.

5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.

MOTOROLA

11

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