MC88LV926 データシートの表示（PDF） - Motorola => Freescale

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MC88LV926

LOW SKEW CMOS PLL CLOCK 68060 DRIVER

Motorola => Freescale 

INTERNAL

LOGIC

RST_OUT PIN

VCC

1K

CL

MC88LV926

ANALOG GND

Figure 3. RST_OUT Test Circuit

12.5MHz

CRYSTAL

OSCILLATOR

SYNC

MR

PLL_EN

RST_IN

2X_Q

Q0

Q1

Q2

Q3

QCLKEN

RST_OUT

66MHz P–CLOCK OUT-

PUT

33MHz

B–CLOCK

AND SYSTEM

OUTPUTS

DELAY 33MHz CLKEN OUTPUT

Figure 4. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships

SYNC Input

tSKEWall

tSKEWf

tCYCLE SYNC Input

tSKEWr

tSKEWf

tSKEWr

Q0–Q3 Outputs

2X_Q Output

tCYCLE ‘Q’ Outputs

QCLKEN

tSKEWQCLKEN

tSKEWQCLKEN

Figure 5. Output/Input Switching Waveforms and Timing Relationships

Timing Notes

1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%

duty cycle.

2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as

‘windows’, not as a ± deviation around a center point.

TIMING SOLUTIONS

7

BR1333 — REV 5

MOTOROLA

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