HI3086EVAL(1997) データシートの表示（PDF） - Intersil

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HI3086EVAL
(Rev.:1997)

6-Bit, 140 MSPS, Flash A/D Converter

Intersil 

HI3086

Test Circuits (Continued)

+V

S2

+-

S1: ON WHEN A < B

S1 S2: ON WHEN A > B

VIN

DVM

HI3086

-V

A<B A>B

COMPARATOR

6

A6 B6

TO TO

6

BUFFER

A1 B1

A0 B0

“0”

“1”

CONTROLLER

00...00

TO

11..10

FIGURE 5. INTEGRAL LINEARITY ERROR MEASUREMENT

CIRCUIT DIFFERENTIAL LINEARITY ERROR MEA-

SUREMENT CIRCUIT

VRT

VIN

VRB

CLK

∆ν

∆t

VIN

33

32

31

σ (LSB)

30

29

CLK

SAMPLING TIMING FLUCTUATION

(= APERTURE JITTER)

NOTE: Where σ (LSB) is the deviation of the output codes when the

largest slew rate point is sampled at the clock which has exactly the

same frequency as the analog input signal, the aperture jitter Tai is:

tAJ

=

σ/

∆-∆----Tυ--

=

σ/





6--2--4--

x2πf .

FIGURE 6. APERTURE JITTER MEASUREMENT METHOD

SIGNAL

VIN

SOURCE

fC

4

-1kHz

2VP-P SINE WAVE

HI3086

6

LATCH

CLK

CLK

A COMPARATOR

A>B

B

+

LATCH

PULSE

COUNTER

SIGNAL

SOURCE

fC

4 LSB

1/8

FIGURE 7. ERROR RATE MEASUREMENT CIRCUIT

Operating Modes

The HI3086 has two types of operating modes which are selected with Pin 41 (SELECT).

TABLE 2. OPERATING MODE

OPERATING

MODE

DMUX Mode

SELECT

VCC

MAXIMUM

CONVERSION RATE

140 Mbps

DATA OUTPUT

Demultiplexed Output 70 Mbps

CLOCK OUTPUT

The input clock is 1/2 frequency

divided and output at 70MHz.

Straight Mode

GND

100 Mbps

Straight Output 100 Mbps

The input clock is inverted and

output at 100MHz.

Demux Mode (See Figures 19, 20, 21).

Set the SELECT pin to VCC for this mode. In this mode, the

clock frequency is divided by 2 in the IC, and the data is out-

put after being demultiplexed by

clock. The 1/2 frequency divided

this 1/2 frequency divided

clock, which has adequate

setup time and hold time for the output data, is output from

the CLKOUT pin.

When using multiple HI3086 units in parallel in this mode, dif-

ferences in the start timing of the 1/2 frequency divided clock

may cause operation as shown in Figures 8 and 9. As a coun-

termeasure, the HI3086 is equipped with a function which

resets the 1/2 frequency divided clock. When resetting this

clock, the RESET pulse must be input to the RESET pin. See

the Timing Charts for the RESET pulse input timing. The A/D

converter can operate at fC (Min) = 140 MSPS in this mode.

4-1415

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