MCF51JF128(2011) データシートの表示（PDF） - Freescale Semiconductor

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MCF51JF128
(Rev.:2011)

Embedded - Microcontrollers

Freescale Semiconductor 

Symbol

IDD_VLLS1

IDD_OSC

Nonswitching electrical specifications

Table 5. Power consumption operating behaviors (continued)

Description

Very low-leakage stop mode 1 current at 3.0 V

• @ –40 to 25 °C

• @ 70 °C

• @ 105 °C

Min.

—

—

—

Typ.

1.3

TBD

TBD

Max.

TBD

TBD

TBD

Unit

Notes

10,11

μA

μA

μA

Average current for OSC enabled with 32 kHz

crystal at 3.0 V

—

0.7

—

μA

• @ –40 to 25 °C

—

TBD

—

μA

• @ 70 °C

—

TBD

—

μA

• @ 105 °C

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.

3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but

peripherals are not in active operation.

4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, and

peripherals are in active operation.

5. 25 MHz core and system clocks, and 12.5 MHz bus clock. MCG configured for FEI mode.

6. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.

7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.

Code executing from flash memory.

8. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled,

but peripherals are not in active operation. Code executing from flash memory.

9. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled.

10. OSC clocks disabled.

11. All pads disabled.

12. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For

devices with 8 KB of RAM, power consumption is reduced by 750 nA.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)

• All peripheral clocks disabled except FTFL

• LVD disabled, USB voltage regulator disabled

• No GPIOs toggled

• Code execution from flash memory

DIAGRAM TBD

Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled

The following data was measured under these conditions:

• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)

• All peripheral clocks enabled, but peripherals are not in active operation

MCF51JF128 Advance Information Data Sheet, Rev. 2, 05/2011.

Freescale Semiconductor, Inc.

Preliminary

15

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