MCF51JF128(2011) データシートの表示（PDF） - Freescale Semiconductor

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MCF51JF128
(Rev.:2011)

Embedded - Microcontrollers

Freescale Semiconductor 

Nonswitching electrical specifications

5.3 Switching electrical specifications

Table 8. Device clock specifications

Symbol

fSYS

fSYS_USB

fBUS

FB_CLK

fLPTMR

fSYS

fBUS

FB_CLK

fLPTMR

Description

Normal run mode

System and core clock

System and core clock when USB in operation

Bus clock

Mini-FlexBus clock

LPTMR clock

VLPR mode

System and core clock

Bus clock

Mini-FlexBus clock

LPTMR clock

Min.

—

20

—

—

—

—

—

—

—

Max.

50

—

25

25

25

2

1

1

25

Unit

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

Notes

5.3.1 General Switching Specifications

These general purpose specifications apply to all signals configured for EGPIO, MTIM,

CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,

and full temperature range. The GPIO are set for high drive, no slew rate control, and no

input filter, digital or analog, unless otherwise specified.

Table 9. EGPIO General Control Timing

Symbol

Description

G1

Bus clock from CLK_OUT pin high to GPIO output valid

G2

Bus clock from CLK_OUT pin high to GPIO output invalid

(output hold)

G3

GPIO input valid to bus clock high

G4

Bus clock from CLK_OUT pin high to GPIO input invalid

GPIO pin interrupt pulse width (digital glitch filter disabled)

Synchronous path1

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter enabled)

Asynchronous path2

Min.

—

1

28

—

1.5

100

Max.

32

—

—

4

—

—

Unit

ns

ns

ns

ns

Bus

clock

cycles

ns

Table continues on the next page...

MCF51JF128 Advance Information Data Sheet, Rev. 2, 05/2011.

Freescale Semiconductor, Inc.

Preliminary

17

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