MCM56824A データシートの表示（PDF） - Motorola => Freescale
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MCM56824A Datasheet PDF : 10 Pages
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WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1)
MCM56824A–20 MCM56824A–25 MCM56824A–35
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
Write Cycle Time
tAVAV
20
—
25
—
35
—
ns
Address Setup Time
tAVE1L
0
—
0
—
0
—
ns
2
tAVE2H
MUX Control Setup Time
tVSVE1L
0
—
0
—
0
—
ns
2
tVSVE2H
Address Valid to End of Write
tAVE1H
15
—
20
—
30
—
ns
2
tAVE2L
MUX Control Valid to End of Write
tVSVE1H 15
—
20
—
30
—
ns
2
tVSVE2L
Chip Enable to End of Write
tE1LE1H
12
—
15
—
20
—
ns
2, 3
tE2HE2L
Data Valid to End of Write
tDVE1H
8
tDVE2L
—
10
—
15
—
ns
2
Data Hold Time
tE1HDX
0
—
0
—
0
—
ns
2, 4
tE2LDX
Write Recovery Time
tE1HAX
0
—
0
—
0
—
ns
2
tE2LAX
MUX Control Recovery Time
tE1HVSX
0
—
0
—
0
—
ns
2
tE2LVSX
NOTES:
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
A (ADDRESS)
V/S (MUX CONTROL)
E1 (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
E1 OR E2 INITIATED WRITE CYCLE
tAVAV
tAVE1H
tE1HAX
tAVE1L
tVSVE1H
tE1LE1H
tVSVE1L
tDVE1H
tE1HVSX
DATA VALID
tE1HDX
HIGH–Z
MCM56824A
6
MOTOROLA FAST SRAM
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