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MCM63P636 データシートの表示(PDF) - Motorola => Freescale

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MCM63P636 Datasheet PDF : 27 Pages
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READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63P636–250 MCM63P636–225 MCM63P636–200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit Notes
Clock Cycle Time
tKHKH
4
4.4
5
ns
3, 4
Clock High Time
Clock Low Time
Strobe Clock Cycle Time
tKH
1.06
1.24
1.46
ns
4
tKL
1.06
1.24
1.46
ns
4
tSKHSKH
4
4.4
5
ns
3, 4
Strobe Clock High Time
Strobe Clock Low Time
Rising K to Rising SK
tSKH
1.06
1.24
1.46
ns
4
tSKL
1.06
1.24
1.46
ns
4
tKHSKH
1.6
2.4
1.8
2.6
2.1
2.9
3
Clock Access Time
Clock to Output Low–Z
tKHQV
3.9
4.3
4.9
ns
3
tKHQX
0
0
0
ns
5, 6
Clock to Output High–Z
tKHQZ
3.9
4.3
4.9
ns
5, 6
Strobe Clock Access Time
tSKHSTV
3.9
4.3
4.9
ns
3
Setup Times:
Address tAVKH
0.5
0.5
0.5
ns
3
ADS tSVKH
1.2
1.5
1.5
Chip Enable tEVKH
0.5
0.5
0.5
Data In tDVKH
1.2
1.5
1.5
Data Out tQVSTV
1
1.1
1.15
Write tWVKH
1.2
1.5
1.5
Hold Times:
Address tKHAX
4
4.4
5
ns
3
ADS tKHSX
0.5
0.5
0.5
Chip Enable tKHEX
4
4.4
5
Data In tKHDX
0.5
0.5
0.5
Data Out tSTVQX
1
1.1
1.15
Write tKHWX
0.5
0.5
0.5
NOTES:
1. Reads and writes are as defined in the Truth Table.
2. All read and write cycle timings are referenced from K, SK, or data strobes.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. Refer to Figure 5 for input reference levels.
5. This parameter is sampled and not 100% tested.
6. Measured at ± 200 mV from steady state.
VDDQ
VIH
VDDQ/2
VIL
VSS
tKH, tSKH
tKL, tSKL
tKHKH, tSKHSKH
Figure 6. AC Timing Diagram Clock Reference
MOTOROLA FAST SRAM
MCM63P636
11

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