MCM72FB8ML7.5R データシートの表示（PDF） - Motorola => Freescale
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MCM72FB8ML7.5R Datasheet PDF : 20 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time (See Figure 3) . . . . . . . . . 1.0 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
Pipeline
Pipeline
Flow–Through Flow–Through
MCM72PB8ML3.5 MCM72PB8ML4 MCM72FB8ML7.5 MCM72FB8ML8
166 MHz
133 MHz
117 MHz
100 MHz
Parameter
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit Notes
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
Output Enable to Output
Valid
tKHKH
6
—
7.5
—
8.5
—
10
—
ns
tKHKL
2.4
—
3
—
3.4
—
4
—
ns
3
tKLKH
2.4
—
3
—
3.4
—
4
—
ns
3
tKHQV
—
3.5
—
4
—
7.5
—
8
ns
tGLQV
—
3.5
—
3.8
—
3.5
—
3.5
ns
Clock High to Output Active tKHQX1
0
—
0
—
0
—
0
—
ns 4, 5
Clock High to Output
Change
tKHQX2
1.5
—
1.5
—
2
—
2
—
ns
4
Output Enable to Output
tGLQX
0
—
0
—
0
—
0
—
ns 4, 5
Active
Output Disable to Q High–Z tGHQZ
—
3.5
—
3.8
—
3.5
—
3.5
ns 4, 5
Clock High to Q High–Z
tKHQZ
1.5
6
1.5
7.5
2
3.5
2
3.5
ns 4, 5
Setup Times:
Address tADKH
1.5
—
1.5
—
2
—
2
—
ns
ADSP, ADSC, ADV tADSKH
Data In tDVKH
Write tWVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
0.5
—
0.5
—
ns
ADSP, ADSC, ADV tKHADSX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.25 V
Figure 2. AC Test Load
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
9
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