MCP1640 データシートの表示（PDF） - Microchip Technology

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MCP1640

0.65V Start-up Synchronous Boost Regulator with True Output Disconnect or Input/Output Bypass Option

Microchip Technology 

MCP1640/B/C/D

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin No.

MCP1640/B/C/D MCP1640/B/C/D

SOT23

2x3 DFN

Description

SW

1

GND

2

EN

3

FB

4

VOUT

5

VIN

6

SGND

PGND

VOUTS

VOUTP

EP

—

5

Switch Node, Boost Inductor Input Pin

Ground Pin

4

Enable Control Input Pin

1

Feedback Voltage Pin

Output Voltage Pin

8

Input Voltage Pin

2

Signal Ground Pin

3

Power Ground Pin

7

Output Voltage Sense Pin

6

Output Voltage Power Pin

9

Exposed Thermal Pad (EP); must be connected to VSS.

3.1 Switch Node Pin (SW)

Connect the inductor from the input voltage to the SW

pin. The SW pin carries inductor current and can be as

high as 800 mA peak. The integrated N-Channel switch

drain and integrated P-Channel switch source are inter-

nally connected at the SW node.

3.2 Ground Pin (GND)

The ground or return pin is used for circuit ground con-

nection. Length of trace from input cap return, output

cap return and GND pin should be made as short as

possible to minimize noise on the GND pin. In the

SOT23-6 package, a single ground pin is used.

3.3 Enable Pin (EN)

The EN pin is a logic-level input used to enable or

disable device switching and lower quiescent current

while disabled. A logic high (>90% of VIN) will enable

the regulator output. A logic low (<20% of VIN) will

ensure that the regulator is disabled.

3.4 Feedback Voltage Pin (FB)

The FB pin is used to provide output voltage regulation

by using a resistor divider. The FB voltage will be 1.21V

typical with the output voltage in regulation.

3.5 Output Voltage Pin (VOUT)

The output voltage pin connects the integrated

P-Channel MOSFET to the output capacitor. The FB

voltage divider is also connected to the VOUT pin for

voltage regulation.

3.6 Power Supply Input Voltage Pin

(VIN)

Connect the input voltage source to VIN. The input

source should be decoupled to GND with a 4.7 µF

minimum capacitor.

3.7 Signal Ground Pin (SGND)

The signal ground pin is used as a return for the

integrated VREF and error amplifier. In the 2x3 DFN

package, the SGND and power ground (PGND) pins are

connected externally.

3.8 Power Ground Pin (PGND)

The power ground pin is used as a return for the high-

current N-Channel switch. In the 2x3 DFN package, the

PGND and signal ground (SGND) pins are connected

externally.

3.9 Output Voltage Sense Pin (VOUTS)

The output voltage sense pin connects the regulated

output voltage to the internal bias circuits. In the 2x3

DFN package, VOUTS and VOUTP are connected

externally.

3.10 Output Voltage Power Pin (VOUTP)

The output voltage power pin connects the output volt-

age to the switch node. High current flows through the

integrated P-Channel and out of this pin to the output

capacitor and output. In the 2x3 DFN package, VOUTS

and VOUTP are connected externally.

3.11 Exposed Thermal Pad (EP)

There is no internal electrical connection between the

Exposed Thermal Pad (EP) and the PGND and SGND

pins. They must be connected to the same potential on

the Printed Circuit Board (PCB).

 2010 Microchip Technology Inc.

DS22234A-page 9

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