MCP1725 データシートの表示（PDF） - Microchip Technology
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MCP1725 Datasheet PDF : 32 Pages
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MCP1725
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Fixed Output
Adjustable
Output
Name
1
2
3
4
5
6
—
7
8
Exposed Pad
1
2
3
4
5
6
7
—
8
Exposed Pad
VIN
VIN
SHDN
GND
PWRGD
CDELAY
ADJ
Sense
VOUT
EP
Description
Input Voltage Supply
Input Voltage Supply
Shutdown Control Input (active-low)
Ground
Power Good Output (open-drain)
Power Good Delay Set-Point Input
Voltage Sense Input (adjustable version)
Voltage Sense Input (fixed voltage version)
Regulated Output Voltage
Exposed Pad of the DFN Package (ground potential)
3.1 Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3 Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications that have switching or noisy inputs, tie
the GND pin to the return of the output capacitor.
Ground planes help lower inductance and voltage
spikes caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is typically delayed by 200 µs (typical,
no capacitance on CDELAY pin) from the time the LDO
output is within 92% + 3% (max hysteresis) of the
regulated output value on power-up. This delay time is
controlled by the CDELAY pin.
3.5 Power Good Delay Set-Point Input
(CDELAY)
The CDELAY input sets the power-up delay time for the
PWRGD output. By connecting an external capacitor
from the CDELAY pin to ground, the typical delay times
for the PWRGD output can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). This allows
for the optimal setting of the system reset time.
DS22026B-page 14
© 2007 Microchip Technology Inc.
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