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MH8S64BBKG-8 データシートの表示(PDF) - Mitsumi

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MH8S64BBKG-8 Datasheet PDF : 55 Pages
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
Function described
0 Defines # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
6
Data Width of this assembly...
7
... Data Width continuation
8
Voltage interface standard of this assembly
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
-7,7L,-8,8L
tAC for CL=3
-10,10L
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
14
Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
18
CAS# Latency
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A7
2BANK
x64
0
LVTTL
10ns
6ns
8ns
Non-PARITY
self refresh(15.625uS)
x16
N/A
1
1/2/4/8/Full page
4bank
2/3
19
CS# Latency
0
20
Write Latency
0
21
SDRAM Module Attributes
non-buffered,non-registered
22
SDRAM Device Attributes:General
Precharge All,Auto precharge
23
SDRAM Cycle time(2nd highest CAS latency) -7,7L
Cycle time for CL=2
-8,8L
-10,10L
10ns
13ns
15ns
24
SDRAM Access form Clock(2nd highest CAS latency) -7,7L
6ns
tAC for CL=2
-8,8L
7ns
-10,10L
8ns
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
26
SDRAM Access form Clock(3rd highest CAS latency)
N/A
27
Precharge to Active Minimum
-7,7L,-8,8L
20ns
-10,10L
30ns
28
Row Active to Row Active Min.
20ns
29
RAS to CAS Delay Min
-7,7L,-8,8L
20ns
-10,10L
30ns
30
Active to Precharge Min
-7,7L,-8,8L
50ns
-10,10L
60ns
SPD DATA(hex)
80
08
04
0C
08
02
40
00
01
A0
60
80
00
80
10
00
01
8F
04
06
01
01
00
0E
A0
D0
F0
60
70
80
00
00
14
1E
14
14
1E
32
3C
MIT-DS-0291-0.0
MITSUBISHI
ELECTRIC
( 4 / 55 )
21.Dec.1998

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