MH8V7245BWZTJ-6 データシートの表示（PDF） - MITSUBISHI ELECTRIC
部品番号
コンポーネント説明
メーカー
MH8V7245BWZTJ-6
MITSUBISHI ELECTRIC
MH8V7245BWZTJ-6 Datasheet PDF : 24 Pages
| |||
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Symbol
Parameter
tRC
Read cycle time
tRAS /RAS low pulse width
tCAS /CAS low pulse width
tCSH
tRSH
/CAS hold time after /RAS low
/RAS hold time after /CAS low
tRCS Read Setup time after /CAS high
tRCH Read hold time after /CAS low
tRRH Read hold time after /RAS low
tRAL Column address to /RAS hold time
tCAL Column address to /CAS hold time
tORH /RAS hold time after /OE low
tOCH /CAS hold time after /OE low
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22)
(Note 22)
Limits
-5
Min
Max
Min
84
104
50
10000
60
8
10000
10
35
40
13
15
0
0
0
0
0
0
25
30
13
18
13
15
13
15
-6
Max
10000
10000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
Limits
-5
-6
Unit
tWC
Write cycle time
Min
Max
Min
Max
84
104
ns
tRAS /RAS low pulse width
50
10000
60
10000
ns
tCAS
tCSH
tRSH
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
8
10000
35
13
10
10000
ns
40
ns
15
ns
tWCS Write setup time before /CAS low
(Note 24)
0
0
ns
tWCH Write hold time after /CAS low
8
10
ns
tCWL /CAS hold time after /W low
8
10
ns
tRWL /RAS hold time after /W low
8
10
ns
tWP
Write pulse width
8
10
ns
tDS
Data setup time before /CAS low or /W low
0
0
ns
tDH
Data hold time after /CAS low or /W low
8
10
ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
Limits
-5
-6
Unit
Min
Max
Min
Max
tRWC Read write/read modify write cycle time (Note23) 109
133
ns
tRAS /RAS low pulse width
75
10000
89
10000
ns
tCAS /CAS low pulse width
38
10000
44
10000
ns
tCSH /CAS hold time after /RAS low
70
82
ns
tRSH /RAS hold time after /CAS low
38
44
ns
tRCS Read setup time before /CAS low
0
0
ns
tCWD Delay time, /CAS low to /W low
(Note24)
28
32
ns
tRWD Delay time, /RAS low to /W low
(Note24)
65
77
ns
tAWD Delay time, address to /W low
(Note24)
40
47
ns
tOEH /OE hold time after /W low
13
15
ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD ≥tCPWD(min) (for Hyper page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.
MIT-DS-0287-0.0
MITSUBISHI
ELECTRIC
( 8 / 24 )
9/Nov./1998
Share Link: