HV9906 データシートの表示（PDF） - Supertex Inc
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HV9906 Datasheet PDF : 10 Pages
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Functional Description - continued
The voltage difference between the sensed nodes will require the
selection of resistor values in series with the NS and PS pins that
will result in current balance. While balance can be achieved even
if neither sensed node is at ground potential, care must be taken to
assure that the dynamic voltage excursions of the sensed node
within the design operating range (i.e. 50KHz to 250KHz) of the
particular application does not result in common mode current
swings in the PS and NS pins that would result in saturation of the
integrators. Saturation at frequencies below the minimum
operating frequency of the application is permitted* since by design
the circuit will soft start from its lowest frequency.
To regulate on a sense node voltage of +0.5V with respect to
ground connect a 200kΩ resistor from the NS pin to the ground
end of the sense element and a 100kΩ resistor from the PS pin to
the +0.5V end of the sense element. Since the voltage drop on the
200kΩ resistor connected to the NS pin is 1V, a reference current
of 5µA is established. To achieve current balance in the PS pin
the sensed node must rise to +0.5V.
For regulating a sense node voltage of –1V with respect to ground
connect a 200kΩ resistor from the PS pin to the ground end of the
sense element and a 400kΩ resistor from the NS pin to the –1V
end of the sense element. Since the voltage drop on the 200kΩ
resistor connected to the PS pin is 1V, a reference current of 5µA
is established. To achieve current balance in the NS pin the
sensed node must fall to -1V.
For calculating the required resistor values refer to “Programming
the Sense Inputs” in the Design Information section.
Integrator
The differential output current of the differential sense circuit is fed
to two matched internal 20pF capacitors that make up the
differential integrator circuit. The tolerances of these integrated
capacitors are typically ±5%, however, since they are matched,
their absolute values only affect the peak voltage of the integrators.
Operating at the lowest frequency results in the highest peak
voltage on the integrators, which will saturate if the peak voltage
on the capacitors exceeds 6V, resulting in a loss of regulation.
This must be taken into consideration when deciding on the value
of the sense currents in the PS and NS pins. The signals at the
sensed nodes may be discontinuous (i.e. controlling the average
output current into LEDs) since the signals are cycle-averaged by
the differential integrator. The differential output of the integrator is
fed to the sample and hold comparators.
*The circuit soft starts from the lowest frequency, therefore it is
very likely that the integrators will saturate during startup. By
design the VCO frequency will be incremented in the event of a
saturated condition, thereby guaranteeing that the circuit will start.
HV9906
Sample and Hold VCO Control
The cycle-averaged outputs of the differential integrator are
compared by the window comparator of the sample and hold
circuit. If the differential integrator outputs are unequal the sample
and hold circuit increments or decrements the VCO control voltage
by a fixed small step resulting in a shorter or longer subsequent
VCO cycle and thus an increased or decreased frequency. When
the cycle-averaged signals from the differential integrator are
nearly equal (within the hysteresis band of the comparators) the
sample and hold function is halted and the off time is unchanged.
Since the frequency is incremented or decremented in small fixed
steps at the end of each cycle the rate of frequency increase or
decrease is a function of the frequency and thus the oscillator
frequency will change exponentially.
In this manner the Integrator Lock Loop (IL2) feedback controls the
oscillator frequency based on a cycle-averaged sensed value to
maintain output regulation. For certain off-line topologies, the
result is near fixed frequency operation for a fixed load with a
dither of a few KHz which helps in meeting FCC conducted
emission requirements.
Gate Driver
The gate driver buffers the output of the VCO and provides
sufficient gate drive power to achieve rise and fall times below
75nS into a 750pF equivalent MOSFET gate. The under voltage
lockout (UVLO) assures that sufficient voltage is available to drive
the gate of standard or logic level threshold MOSFETs.
Soft Start
On initial power application the UVLO and POR resets the output
latch and sets the VCO to its lowest frequency state, which
represents minimum power transfer per VCO cycle. Thereafter,
the differential sense feedback loop increments the frequency in
small steps, increasing the power transfer rate until output
regulation is achieved, thereby providing the required soft start
function.
5
07/23/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
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