MIC59P60 データシートの表示（PDF） - Micrel

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MIC59P60

8-Bit Serial-Input Protected Latched Driver

Micrel 

MIC59P60

PLCC Pin

Configuration

SERIAL DATA IN 4

VSS 5

VDD 6

SERIAL DATA OUT 7

STROBE 8

32

1 20 19

18 OUT 2

17 OUT 3

MIC59P60BV 16 OUT 4

15 OUT 5

14 OUT 6

9 10 11 12 13

Typical Inputs VDD

V DD

CLOCK

SERIAL

DATA IN

STROBE

OUTPUT

ENABLE

V SS

Typical Output Driver

K

OUT

N

V SS

Micrel

Absolute Maximum Ratings VSS = 0; TA = 25°C

Output Voltage (VCE) .................................................... 80V

Output Voltage (VCE(SUS)) ............................... 50V, Note 1

VDD with Reference to VSS ........................................... 15V

VDD with Reference to VEE ........................................... 25V

Emitter Supply Voltage (VEE) ...................................... –20V

Input Voltage (VIN) ............................... –0.3V to VDD+0.3V

Protected Current ............................................ 1.5A, Note 2

Power Dissipation (PD)

Plastic DIP (N) ......................................................... 2.0W

Derate above TA = +25°C ............................ 20mW/°C

PLCC (V) .................................................................1.4W

Derate above TA = +25°C ............................ 14mW/°C

Wide SOIC (WM) .................................................... 1.2W

Derate above TA = +25°C ............................ 12mW/°C

Operating Temperature (TA)

Plastic DIP (N), PLCC (V), SOIC (WM) .. –40°C to +85°C

Storage Temperature (TS) ....................... –65°C to +150°C

Junction Temperature (TJ) ...................................... +150°C

ESD ......................................................................... Note 3

Note 1:

Note 2:

Note 3:

For inductive load applications.

Each channel. VEE connection must be designed to minimize

inductance and resistance.

Devices are input-static protected but can be damaged by

extremetly high static charges.

Pin Description

3K

VEE

SUB

Pin

1

2,10

3

4

5

6

7

8

9

11

12—19

20

Name

Description

CLEAR

Sets All Latches OFF (open).

VEE

Output Ground (Substrate). Most negative voltage in the system connects

here.

CLOCK

Serial Data Clock. A CLEAR must also be clocked into the latches.

SERIAL DATA IN

Serial Data Input pin.

VSS

VDD

SERIAL DATA OUT

Logic reference (Ground) pin.

Logic Positive Supply voltage.

Serial Data Output pin. (Flow through).

STROBE

Output Strobe pin. Loads output latches when High. A STROBE is needed

to CLEAR latches.

OUTPUT ENABLE/RESET When Low, Outputs are active. When High, device is inactive and reset

from a fault condition. An under voltage condition emulates a high OE/

RESET input.

K

Transient suppression diode's cathode common pin.

OUTPUT N

Open Collector outputs 8 through 1.

FLAG

Error Flag. Open-collector output is Low upon Overcurrent Fault or

Overtemperature fault. OUTPUT ENABLE/RESET must be pulled high to

reset the flag and fault condition.

MIC59P60

2

August 2001

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