MK2049-02 データシートの表示（PDF） - Integrated Circuit Systems

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MK2049-02

Communications Clock PLLs

Integrated Circuit Systems 

MK2049-02/03

Communications Clock PLLs

INPUT AND OUTPUT SYNCHRONIZATION (continued)

MK2049-03

As illustrated in the diagram below, when using the MK2049-03 in one of the Zero Delay selections, the

rising edge of ICLK will be aligned with the rising edges of CLK1 and CLK2.

ICLK (8 kHz)

CLK2 (MHz)

CLK1 (MHz)

Figure 2. MK2049-03 Input and Output Clock Waveforms in Zero Delay Selections

In the MK2049-02 and MK2049-03 selections that are not Zero Delay, the phase relationship between the

input and output clocks is not predictable. Although it will not change once the MK2049-02/03 is running,

this relationship is likely to change when power is interrupted.

Measuring Zero Delay on the MK2049

The MK2049-02/03 both produce low-jitter output clocks. In addition, both parts have a very low

bandwidth--on the order of a few Hertz. Since most 8 kHz input clocks will have high jitter, this can make

measuring the input-to-output skew (zero delay feature) very difficult. The MK2049 are designed to reject

the input jitter; when the input and output clocks are both displayed on an oscilloscope, they may appear

not to be locked because the scope trigger point is constantly changing with the input jitter. In fact, the

input and output clocks probably are locked, and the MK2049 will have zero delay to the average position

of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab

frequency sources are NOT SUITABLE for this since they have high jitter at low frequencies.

Frequency Locking to the Input

In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified

output frequency as long as the combined variation of the input frequency and the crystal does not exceed

100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the

input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.

MDS 2049-02/03 B

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Revision 040601

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