ML2722 データシートの表示（PDF） - Micro Linear Corporation

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ML2722

900MHz Low-IF 1.5Mbps FSK Transceiver

Micro Linear Corporation 

7 TPC/TPQ

O (Open

Drain)

Transmit power control output. This

open-drain output is pulled low when the

TPC bit in serial register #0 is set.

Transitions on TPC are synchronized to

the falling edge of RXON. In analog test

modes, this pin and the RSSI output

become test access points controlled by

the serial control bus.

ML2722

TPQ

MUX

VDD

31

TPC

TPC

MUX

100Ω

7 TPC/TPQ

9 REF

8

8

VSS

VSS

I

Input for the 12.288MHz or 6.144MHz

VCC5

reference frequency. This input is used

24

as the reference frequency for the PLL

and as a calibration frequency for the on-

chip filters. This is a self-biased CMOS

input that is designed to be driven either

by an AC-coupled sine wave.

9

40k

REF

11 QPO

O

Charge Pump Output of the phase

detector. This is connected to the

external PLL loop filter.

40k

RVCC1

10

8

VSS

VCC5

24

11 QPO

8

VSS

DS2722-F-06

FINAL DATASHEET

DECEMBER 2005 11

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