ML6651 データシートの表示（PDF） - Micro Linear Corporation

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ML6651

Auto-Negotiating Media Converter

Micro Linear Corporation 

ADVANCED

ML6651

PIN DESCRIPTIONS (continued)

Pin # Signal Name Description

38

RTTP

Twisted pair or LVPECL/PECL compatible driver bias resistor. An external resistor connected

between RTTP and ground sets a constant bias current for the differential output driver circuitry.

These output currents depend on the operating mode.

The recommended external component values are:

Twisted pair mode:

2KW, 1 %, between RTTP and ground.

50W, 1 %, between TPOUTP and VCC

50W, 1 %, between TPOUTN and VCC

LVPECL/PECL compatible mode:

2KW, 1 %, between RTTP and ground.

62W, 1 %, between TPOUTP and VCC

62W, 1 %, between TPOUTN and VCC

Also AC couple to the PMD inputs

10

TPINP

Two operating modes are available for these pins and are selected with the configuration pin

PECLTP or the configuration bit LVPECLTP (bit 30.3).

11

TPINN

Twisted Pair Interface Mode:

Receive twisted pair positive and complementary inputs. These inputs form a differential input

pair that receives 100BASE-TX, FLP Burst, or 10BASE-T signal from the network. The common

mode voltage is set internally and the input impedance is about 10KW.

LVPECL/PECL Compatible Interface Mode:

LVPECL or PECL compatible interface positive and complementary inputs. These inputs form a

differential input pair that receives 100BASE-FX, 100BASE-SX, FLNP Bursts, or 10BASE-FL signal

from a fiber optic PMD. The PMD outputs are AC coupled to these inputs with .1mF capacitors.

The common mode voltage is set internally with resistors of about 1KW from each input pin to an

on-chip voltage reference. The positive output of the PMD (high during the high-light state) must

connect to TPINP and the complementary output of the PMD must connect to TPIN

37

REQSD

Twisted Pair Interface Mode:

Equalizer bias resistor pin. An external resistor connected between this pin and ground sets

internal currents that control the receiver’s adaptive equalizer transfer function. The voltage at

this pin is PTAT. It’s nominal value is 1.2V and it’s range is .9V to 1.5V. The recommended resistor

value is 5KW, 1 %

LVPECL/PECL Compatible Interface Mode:

This input pin is connected to the Signal Detect (SD) output of a fiber optic PMD module. The

voltage level at this pin is compared to the voltage level at pin SDTH to determine the logic

value. If it is lower, then the input at TPINP/TPINN is rejected. If it is higher, then the input at

TPINP/TPINN is passed to the internal circuits.

39

SDTH

The voltage at this pin is a single ended LVPECL/PECL reference. Refer to description of SDFO

and REQSD pins.

This pin is not used if neither the TPINP/TPINN interface, nor the FOINP/FOINN are setup for

LVPECL/PECL compatible mode. In such a case, the SDTH pin must be connected to any

potential between VCC and Ground.

21

IOUT

2 operating modes are available for these pins and are selected with the configuration pin

“PECL_QU” or the configuration bit “LVPECLQU” (bit 30.7).

September 2000 Advanced Datasheet

5

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