ML6651 データシートの表示（PDF） - Micro Linear Corporation
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ML6651 Datasheet PDF : 10 Pages
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ADVANCED
ML6651
PIN DESCRIPTIONS (continued)
Pin # Signal Name Description
8
PECLQU This pin sets the Media Converter to interface at pins FOINP/FOINN and IOUT /IOUT, to an
external PECL or LVPECL PMD, or to an LED and a fiber optic receiver.
When using an LED and fiber optic receiver, this pin also indicates the maximum supported link
distance. When the 300m maximum link length is selected, the voltage thresholds for Signal
Detect are increased.
4
AD4LIW Determines the value of the PHY address bit 4 for accessing the Serial Management Interface,
and determines if the Link Integrity Warning (LIW) function is enabled or disabled.
The Link Integrity Warning (LIW) function can only be enabled when only one SPEED is
available through setting of pin SPEED and/or management registers. When LIW is enabled and
the input link is down at one interface to the Media Converter, the transmitter output on that
interface is turned off for about 425ms every 3.8 seconds (or 104ms every 934ms, when the
TestFast bit 28.0 is 1). It applies to both network interfaces and both data rates. Notice that if the
link at the other interface to the Media Converter is also down, there is never an output. The
LIW function causes the Link Up indicator of the link partner to blink.
5
AD32
Determines the value of the PHY address bits 3 and 2 for accessing the Serial Management
Interface.
6
AD10
Determines the value of the PHY address bits 1 and 0 for accessing the Serial Management
Interface.
25
DUPLEX This DUPLEX input can have one of three (3) levels. VCC, VCC/2 and 0Volt.
DUPLEX input has 80KW resistors to VCC and Ground. With the input floating the input voltage
is VCC/2. Left open the Transparent mode of operation is enabled.
VCC or 0Volt at the DUPLEX input enables the Non-Transparent mode of operation
27
SPEED
This SPEED input can have one of three (3) levels: VCC, VCC/2, and 0Volt.
VCC input enables only 100Mb/s operation. 10Mb/s and Auto-Negotiation are disabled.
Duplex operation is also disabled.
SPEED input has 80KW resistor to VCC and Ground. With the input floating the input voltage is
VCC/2. Left open, this mode enables 100Mb/s and 10Mb/s operation. The Duplex mode
enables Transparent or Non-Transparent mode operation. Link Integrity Warning (LIW) can be
enabled.
0Volt input on SPEED enables only 10Mb/s operation. 100Mb/s and Auto-Negotiation are
disabled. Duplex operation is also disabled
13 TPOUTOFF When this input is low, the output stage of the twisted pair output is turned off. CMOS input.
14 FOOUTOFF When this input is low, the output stage of the fiber optic output is turned off. CMOS input.
24 PWRDWN When this input is low, all the circuits are powered down. Configuration pins are read and
register bits are initialized, 3 to 8ms after a rising edge of PWRDWN. CMOS input.
18 REFCLOCK 25MHz Reference clock CMOS input. This clock is used for internal digital logic, and as a
reference for the PLLs.
2
GNDT
Ground for the twisted pair driver output stage.
12
GNDE
Ground for the equalizer, one PLL and part of the descrambler and twisted pair driver.
15
GNDD
Ground for CMOS noisy circuits.
20
GNDL
Ground for the fiber optic LED driver output stage.
8
Advanced Datasheet September 2000
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