ML9227 データシートの表示（PDF） - Oki Electric Industry
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ML9227
Oki Electric Industry
ML9227 Datasheet PDF : 26 Pages
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OKI Semiconductor
FEDL9227-01
ML9227
PIN DESCRIPTIONS
Pin
1, 51
8
26
24
33
40 to 50,
52 to 59
60 to 64,
2 to 4
5, 6, 7
29
28
27
22
23
34 to 39
20, 21
14 to 18
9 to 13
Symbol
VDISP
D-GND
L-GND
VCC
VREG
SEG1 to 19
SEG20 to 27
GRID1 to 3
CS
CLOCK
DATA l/O
INT
DUP/TRl
CH1 to 6
A1, B1
COL1 to 5
ROW1 to 5
Type
—
—
—
O
O
O
O
O
l
l
l/O
O
l
l
O
l
O
Description
Power supply pins
Pin1 and pin51 should be connected externally.
D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for
the logic circuit. Pins 8 and 26 should be connected externally.
5 V output pin for internal logic portion and external logic circuit
Reference voltage (5 V) output pin for A/D converter
Segment (anode) signal output pins for a VFD tube
These pins can be directly connected to the VFD tube. External circuit is
not required.
lOH ≤ –5 mA
Segment (anode) signal output pins for a VFD tube
These pins can be directly connected to the VFD tube. External circuit is
not required.
lOH ≤ –10 mA
Inverted Grid signal output pins
For pre-driver, the external circuit is required.
lOL ≤ 10 mA
Chip Select input pin
Data input/output operation is valid when this pin is set at a High level.
Serial clock input pin
Data is input and/or output through the DATA l/O pin at the rising edge of
the serial clock.
Serial data input/output pin
Data is input to/comes out from the shift register at the rising edge of the
serial clock.
Interrupt signal output to micro controller. When any key of key matrix is
pressed or released, key scanning is started. After the completion of the
one cycle, this pin goes to high level and keeps the high level until key
scan stop mode is selected.
Duplex/Triplex operation select input pin
Duplex (1/2 duty) operation is selected when this pin is set at a VCC level.
Triplex (1/3 duty) operation is selected when this pin is set at a GND
level.
Analog voltage input pin for the 8-bit A/D converter
Input pin for the encoder type rotary switch. The phase of an An/Bn input
is detected.
Return inputs from the key matrix
These pins are active low. When key matrix are in the inactive sate,
these pins are at high level through the internal pull-up resistors. All the
inputs do not have the chattering absorption function for the key scans.
Key switch scanning outputs
Normally low level is output through these pin. When any switch of key
matrix is depressed or released, key scanning is started and is continued
until key scan stop mode is selected. When key scan stop mode is
selected, all outputs of ROW1 to 5 go back to low level.
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