ML9261A データシートの表示（PDF） - Oki Electric Industry
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ML9261A Datasheet PDF : 16 Pages
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OKI Semiconductor
FEDL9261A-01
ML9261A
AC Characteristics-1
Parameter
CLK Pulse Width
DIN Setup Time
DIN Hold Time
CLK-LS Setup Time
LS-CLK Setup Time
CLK-LS Hold Time
LS-CHG Setup Time
LS-CL Setup Time
LS Pulse Width
CHG Pulse Width
CL Pulse Width
DOUT Delay time
Driver Output Delay Time
Driver Output Slew Rate
AC Characteristics-2
Parameter
CLK Pulse Width
DIN Setup Time
DIN Hold Time
CLK-LS Setup Time
LS-CLK Setup Time
CLK-LS Hold Time
LS-CHG Setup Time
LS-CL Setup Time
LS Pulse Width
CHG Pulse Width
CL Pulse Width
DOUT Delay time
Driver Output Delay Time
Driver Output Slew Rate
Symbol
tW (CLK)
tSU (D-CLK)
tH (CLK-D)
tSU (CLK-LS)
tSU (LS-CLK)
tSU (L-CLK)
tH (CLK-L)
tSU (LS-CHG)
tSU (LS-CL)
tW (LS)
tW (CHG)
tW (CL)
tPD, tPRD
tDLH
tDHL
tDRHL
tTLH
tTHL
(VDD = 4.5 to 5.5 V, VDISP = 20 to 60 V, Ta = –40 to +85°C)
Condition
Min. Max. Unit
—
80
150
ns
—
50
—
ns
—
50
—
ns
—
50
—
ns
During normal operation
50
—
ns
At display data reset
50
—
ns
At display data reset
50
—
ns
—
50
—
ns
—
50
—
ns
—
80
—
ns
—
10
—
µs
—
10
—
µs
Load: 30 pF
—
50
ns
VDISP = 40 V
—
Load: 1.0 kΩ resistance in
—
parallel with 20 pF capacitance —
2.0
µs
2.0
µs
2.0
µs
VDISP = 40 V
—
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance
—
5.0
µs
5.0
µs
Symbol
tW (CLK)
tSU (D-CLK)
tH (CLK-D)
tSU (CLK-LS)
tSU (LS-CLK)
tSU (L-CLK)
tH (CLK-L)
tSU (LS-CHG)
tSU (LS-CL)
tW (LS)
tW (CHG)
tW (CL)
tPD, tPRD
tDLH
tDHL
tDRHL
tTLH
tTHL
(VDD = 3.0 to 3.6 V, VDISP = 20 to 60 V, Ta = –40 to +85°C)
Condition
Min. Max. Unit
—
80
150
ns
—
50
—
ns
—
50
—
ns
—
50
—
ns
During normal operation
50
—
ns
At display data reset
50
—
ns
At display data reset
50
—
ns
—
50
—
ns
—
50
—
ns
—
80
—
ns
—
10
—
µs
—
10
—
µs
Load: 30 pF
—
50
ns
VDISP = 40 V
—
Load: 1.0 kΩ resistance in
—
parallel with 20 pF capacitance —
3.0
µs
3.0
µs
3.0
µs
VDISP = 40 V
—
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance
—
5.0
µs
5.0
µs
8/16
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