MMBF4392L データシートの表示（PDF） - ON Semiconductor

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MMBF4392L

JFET Switching Transistors

ON Semiconductor 

MMBF4391L, MMBF4392L, MMBF4393L

NOTE 1

RGEN

50 W

VGEN

SET VDS(off) = 10 V

INPUT RK

RGG

50

W

VGG

VDD

RD

RT

50

W

INPUT PULSE

tr ≤ 0.25 ns

tf ≤ 0.5 ns

PULSE WIDTH = 2.0 ms

DUTY CYCLE ≤ 2.0%

RGG > RK

RD' = RD(RT + 50)

RD + RT + 50

Figure 5. Switching Time Test Circuit

OUTPUT

The switching characteristics shown above were measured using

a test circuit similar to Figure 5. At the beginning of the switching

interval, the gate voltage is at Gate Supply Voltage (−VGG). The

Drain−Source Voltage (VDS) is slightly lower than Drain Supply

Voltage (VDD) due to the voltage divider. Thus Reverse Transfer

Capacitance (Crss) of Gate−Drain Capacitance (Cgd) is charged to

VGG + VDS.

During the turn−on interval, Gate−Source Capacitance (Cgs)

discharges through the series combination of RGen and RK. Cgd must

discharge to VDS(on) through RG and RK in series with the parallel

combination of effective load impedance (R’D) and Drain−Source

Resistance (rDS). During the turn−off, this charge flow is reversed.

Predicting turn−on time is somewhat difficult as the channel

resistance rDS is a function of the gate−source voltage. While Cgs

discharges, VGS approaches zero and rDS decreases. Since Cgd

discharges through rDS, turn−on time is non−linear. During turn−off,

the situation is reversed with rDS increasing as Cgd charges.

The above switching curves show two impedance conditions; 1)

RK is equal to RD’ which simulates the switching behavior of

cascaded stages where the driving source impedance is normally the

load impedance of the previous stage, and 2) RK = 0 (low

impedance) the driving source impedance is that of the generator.

20

10

MMBF4393

7.0

5.0

MMBF4392

Tchannel = 25°C

VDS = 15 V

MMBF4391

3.0

2.0

0.5 0.7 1.0

2.0 3.0 5.0 7.0 10 20 30 50

ID, DRAIN  CURRENT (mA)

Figure 6. Typical Forward Transfer Admittance

200 IDSS 25 mA

= 10

160 mA

50 mA

75 mA 100 mA

125 mA

120

80

40

Tchannel = 25°C

0

0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, GATE-SOURCE VOLTAGE (VOLTS)

Figure 8. Effect of Gate−Source Voltage

on Drain−Source Resistance

15

10

Cgs

7.0

5.0

Cgd

3.0

Tchannel = 25°C

2.0

(Cds is negligible

1.5

1.0

0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10

30

VR, REVERSE VOLTAGE (VOLTS)

Figure 7. Typical Capacitance

2.0

1.8

ID = 1.0 mA

VGS = 0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

-70

-40 -10 20 50 80 110 140 170

Tchannel, CHANNEL TEMPERATURE (°C)

Figure 9. Effect of Temperature on Drain−Source

On−State Resistance

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