MP1541DJ データシートの表示（PDF） - Monolithic Power Systems
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MP1541DJ Datasheet PDF : 8 Pages
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Compensation
The MP1541 uses an amplifier to compensate
the feedback loop rather than a traditional
transconductance amplifier like most current
mode regulators. Frequency compensation is
provided by an internal resistor and capacitor
along with an external resistor. The system
uses two poles and one zero to stabilize the
control loop. The poles are fP1 set by the output
capacitor and load resistance, and fP2 set by the
internal compensation capacitor Cc, the gain of
the error amplifier and the resistance seen
looking out at the feedback node REQ. The zero
fZ1 is set internally around 20kHz. These are
determined by the equations:
fP1
=
1
π × C2 × RLOAD
( ) fP2
=
2×π×
1
7.9 × 10−9
× REQ
fZ1 = 20kHz
Where RLOAD is the load resistance and REQ is:
REQ
= R3 +
(R1× R2)
(R1+ R2)
Where R1, R2, and R3 are seen in Figure 2.
The DC loop gain is:
A VDC
=
500 ∗
VIN
∗ RLOAD ∗ VFB
VOUT 2
There is also a right-half-plane zero (fRHPZ) that
exists in all continuous mode (inductor current
does not drop to zero on each cycle) step up
converters. The frequency of the right half plane
zero is:
fRHPZ
=
VIN2 × RLOAD
2 × π × L × VOUT 2
MP1541 – 1.3MHz BOOST CONVERTER
To stabilize the regulation control loop, the
crossover frequency (the frequency where the
loop gain drops to 0dB or a gain of 1, indicated
as fC) should be at least one decade below the
right-half-plane zero and should be at most
75kHz. fRHPZ is at its lowest frequency at
maximum output load current (RLOAD is at a
minimum) and minimum input voltage.
For the MP1541 it is recommended that a 47kΩ
to 100kΩ resistor be placed in series with the FB
pin and the resistor divider as seen in Figure 2.
For most applications this is all that is needed for
stable operation. If greater phase margin is
needed a series resistor and capacitor can be
placed in parallel with the high-side resistor R1 as
seen in Figure 2. The pole and zero set by the
lead-lag compensation network are:
fP3 =
1
⎜⎛
2 × π × C3 × ⎜R4 +
1
⎟⎞
⎟
⎜
⎜⎝
1
R1
+
1
R2
+
1
R3
⎟
⎟⎠
fZ2
=
1
2 × π × C3 × (R1+ R4)
LAYOUT CONSIDERATIONS
High frequency switching regulators require
very careful layout for stable operation and low
noise. All components must be placed as close
to the IC as possible. Keep the path between
L1, D1, and C2 extremely short for minimal
noise and ringing. C1 must be placed close to
the IN pin for best decoupling. All feedback
components must be kept close to the FB pin to
prevent noise injection on the FB pin trace. The
ground return of C1 and C2 should be tied
close to the GND pin. See the MP1541 demo
board layout for reference.
MP1541Rev.1.3
www.MonolithicPower.com
6
3/20/2006
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© 2006 MPS. All Rights Reserved.
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