MP7528JS データシートの表示（PDF） - Exar Corporation

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MP7528JS

CMOS Dual Buffered Multiplying 8-Bit Digital-to-Analog Converter

Exar Corporation 

MP7528

INTERFACE LOGIC INFORMATION

DAC Selection: Both DAC latches share a common 8-bit in-

put port. The control input DACA/DACB selects which DAC can

accept data from the input port.

Mode Selection: Inputs CS and WR control the operating

mode of the selected DAC. See Mode Selection Table below:

Write Mode: When CS and WR are both low the selected

DAC is in the write mode. The input data latches of the selected

DAC are transparent and its analog output responds to activity

on DB0-DB7.

Hold Mode: The selected DAC latch retains the data which

was present on DB0-DB7 just prior to CS and WR assuming a

high state. Both analog outputs remain at the values corre-

sponding to the data in their respective latches.

DAC A/DAC B CS

WR DAC A DAC B

L

L

L

Write

Hold

H

L

L

Hold

Write

X

H

X

Hold

Hold

X

X

H

Hold

Hold

L = LOW state, H = HIGH state, X = Don’t care state

Table 1. Mode Selection Table

CS

DAC A/DAC B

WR

DATA IN VIH

(DB0-DB7) VIL

tCS

tCH

tAS

tAH

tWR

tDS

tDH

VIH DATA IN

VIL STABLE

VDD

0

VDD

0

VDD

0

VDD

0

NOTES:

1. All input signal rise and fall times measured from 10% to 90% of VDD.

VDD = +5 V, tr = tf = 20 ns

VDD = +15 V, tr = tf = 40 ns

2. Timing measurement reference level is VIH + VIL / 2

Figure 1. Write Cycle Timing Diagram

Rev. 2.00

8

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