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MP7542JS データシートの表示(PDF) - Exar Corporation

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MP7542JS Datasheet PDF : 12 Pages
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MP7542
A0 - A1
CS
WR
DB3 - DB0
VINH
VINL
VINH
VINL
ADDRESS BUS VALID
tAWS1
tCWS1
tAWS2
tWR
tAWH
tCWH
tCWS2
tDS
tDH
VINH
VINL
DATA
BUS VALID
Figure 1. Timing Diagram
MP7542 Control Inputs
A1
A0
CS
WR CLR
X
X
X
X
X
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
0
X
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
MP7542 Operation
Resets DAC 12-bit register to code 0000 0000 0000
No operation; device not selected
Load LOW byte data register on edges as shown
Load MIDDLE byte data register on edges as shown
Load HIGH byte data register on edges as shown
Load applicable
data register
with data at
D0 - D3
Load 12-bit DAC register with data in LOW byte, MIDDLE
byte, & HIGH byte data registers
NOTES
1. 1 indicates logic HIGH
2. 0 indicates logic LOW
3. X indicates don’t care
4. indicates LOW to HIGH transition
5. MSB XXXX XXXX XXXX LSB
high middle low
byte byte byte
6. Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to
latch data and using CS as a device enable.
Rev. 2.00
Table 1. Truth Table
5

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