MPC974FA データシートの表示（PDF） - Motorola => Freescale

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MPC974FA

3.3V PLL Clock Driver

Motorola => Freescale 

33MHz

TCLK

FB_In

5

Qa

5

Qb

4

Qc

QFB

66MHz

66MHz

33MHz

33MHz

fsela fselb fselc fselFB VCO_Sel

0

0

0

00

0

MPC974

33MHz

TCLK

FB_In

5

Qa

5

Qb

4

Qc

QFB

100MHz

50MHz

33MHz

33MHz

fsela fselb fselc fselFB VCO_Sel

0

1

1

10

0

25MHz

TCLK

FB_In

5

Qa

5

Qb

4

Qc

QFB

100MHz

50MHz

33MHz

25MHz

fsela fselb fselc fselFB VCO_Sel

0

1

1

01

0

50MHz

TCLK

FB_In

5

Qa

5

Qb

4

Qc

QFB

50MHz

50MHz

50MHz

50MHz

fsela fselb fselc fselFB VCO_Sel

1

1

0

00

0

Figure 3. MPC974 Programming Schemes

To minimize part–to–part skew the external feedback

option again should be used. The PLL in the MPC974

decouples the delay of the device from the propagation delay

variations of the internal gates. From the specification table

one sees a Tpd variation of only ±150ps, thus for multiple

devices under identical configurations the part–to–part skew

will be around 850ps (300ps for Tpd variation plus 350ps

output–to–output skew plus 200ps for jitter). To minimize this

value, the highest possible reference frequencies should be

used. Higher reference frequencies will minimize both the tpd

parameter as well as the input to output jitter.

Power Supply Filtering

The MPC974 is a mixed analog/digital product and

exhibits some sensitivities that would not necessarily be seen

on a fully digital product. Analog circuitry is naturally

susceptible to random noise, especially if this noise is seen

on the power supply pins. The MPC974 provides separate

power supplies for the output buffers (VCCO) and the internal

PLL (VCCA) of the device. The purpose of this design

technique is to try and isolate the high switching noise digital

outputs from the relatively sensitive internal analog

phase–locked loop. In a controlled environment such as an

evaluation board this level of isolation is sufficient. However,

in a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

power supply filter on the VCCA pin for the MPC974.

3.3V

RS=5–15Ω

VCCA

MPC974

0.01µF

22µF

VCC

0.01µF

Figure 4. Power Supply Filter

Figure 4 illustrates a typical power supply filter scheme.

The MPC974 is most susceptible to noise with spectral

content in the 1KHz to 1MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop that will be seen between the VCC supply and the VCCA

pin of the MPC974. From the data sheet the IVCCA current

(the current sourced through the VCCA pin) is typically 15mA

(20mA maximum), assuming that a minimum of 3.0V must be

maintained on the VCCA pin very little DC voltage drop can

be tolerated when a 3.3V VCC supply is used. The resistor

shown in Figure 4 must have a resistance of 10–15Ω to meet

TIMING SOLUTIONS

5

BR1333 — Rev 6

MOTOROLA

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