MPC9774 データシートの表示（PDF） - Motorola => Freescale
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MPC9774 Datasheet PDF : 16 Pages
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MPC9774
Table 8. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 85°C)a b
Symbol
Characteristics
Min
fref
Input reference frequency
÷8 feedback 25.0
÷12 feedback 16.6
÷16 feedback 12.5
÷24 feedback 8.33
÷32 feedback 6.25
÷48 feedback 4.16
Typ
Max
Unit
Condition
62.5
41.6
31.25
20.83
15.625
10.41
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fVCO
fMAX
Input reference frequency in PLL bypass modec
VCO frequency ranged
200
Output Frequency
÷4 output 50.0
÷8 output 25.0
÷12 output 16.6
÷16 output 12.5
÷24 output 8.33
TBD
500
125.0
62.5
41.6
31.25
20.83
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL bypass
PLL locked
frefDC
tr, tf
Reference Input Duty Cycle
CCLKx Input Rise/Fall Time
40
60
%
1.0
ns 0.8 to 2.0V
t(∅)
Propagation Delay (static phase offset)
CCLKx or FB_IN
±150
ps PLL locked
tsk(O)
DC
Output-to-output Skewe
Output duty cycle
300
ps
45
50
55
%
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
BW
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthg
0.1
RMS (1 σ)f
RMS (1 σ)
RMS (1 σ)
TBD
TBD
TBD
1.0
ns 0.55 to 2.4V
8
ns
8
ns
ps
ps
ps
kHz
tLOCK
Maximum PLL Lock Time
10
ms
a All AC characteristics are design targets and subject to change upon device characterization.
b AC characteristics apply for parallel output termination of 50Ω to VTT.
c In bypass mode, the MPC9774 divides the input reference clock.
d The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M ⋅ VCO_SEL).
e See application section for part-to-part skew calculation.
f See application section for a jitter calculation for other confidence factors than 1 σ.
g -3 dB point of PLL transfer characteristics.
MOTOROLA
6
TIMING SOLUTIONS
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