MPC9992 データシートの表示（PDF） - Motorola => Freescale

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MPC9992

3.3V Differential ECL/PECL PLL Clock Generator

Motorola => Freescale 

MPC9992

APPLICATIONS INFORMATION

SYNC Output Description

The MPC9992 has a system synchronization pulse output

QSYNC. In configurations with the output frequency

relationships are not integer multiples of each other QSYNC

provides a signal for system synchronization purposes. The

MPC9992 monitors the relationship between the A bank and

the B bank of outputs. The QSYNC output is asserted (logic

high) one QA period in duration after the coincident rising

edges of the QA and QB outputs. The placement of the pulse

is dependent on the QA and QB output frequencies ratio.

Table 2 shows the waveforms for the QSYNC output. The

QSYNC output is defined for all possible combinations of the

bank A and bank B outputs.

1:1 Mode

QA

QB

QSYNC

VCC

2:1 Mode

QA

QB

QSYNC

3:1 Mode

QA

QB

QSYNC

QA

3:2 Mode

QB

QSYNC

4:3 Mode

QA

QB

QSYNC

Figure 3. QSYNC Timing Diagram

TIMING SOLUTIONS

7

MOTOROLA

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