MPC961C データシートの表示（PDF） - Motorola => Freescale

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MPC961C

Low Voltage Zero Delay Buffer

Motorola => Freescale 

MPC961C

Freescale Semiconductor, Inc.

combination of the line impedances. The voltage wave

launched down the two lines will equal:

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50Ω || 50Ω

Rs = 36Ω || 36Ω

Ro = 14Ω

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.62V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

3.0

OutA

2.5

tD = 3.8956

2.0

In

1.5

OutB

tD = 3.9386

1.0

0.5

0

2

4

6

8

10 12 14

TIME (nS)

Figure 5. Single versus Dual Waveforms

SPICE level and IBIS output buffer models are available

for engineers who want to simulate their specific interconnect

schemes.

Using the MPC961C in zero-delay applications

Nested clock trees are typical applications for the

MPC961C. Designs using the MPC961C as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback option of the

MPC961C clock driver allows for its use as a zero delay

buffer. By using the QFB output as a feedback to the PLL the

propagation delay through the device is virtually eliminated.

The PLL aligns the feedback clock output edge with the clock

input reference edge resulting a near zero delay through the

device. The maximum insertion delay of the device in

zero-delay applications is measured between the reference

clock input and any output. This effective delay consists of

the static phase offset, I/O jitter (phase or long-term jitter),

feedback path delay and the output-to-output skew error

relative to the feedback output.

Calculation of part-to-part skew

The MPC961C zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC961C are connected together, the maximum overall

timing uncertainty from the common CCLK input to any

output is:

tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅)
CF

This maximum timing uncertainty consist of 4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 6. should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

MPC961

OUTPUT

BUFFER

14Ω

RS = 22Ω ZO = 50Ω

RS = 22Ω ZO = 50Ω

14Ω + 22Ω k 22Ω = 50Ω k 50Ω

25Ω = 25Ω

Figure 6. Optimized Dual Line Termination

CCLKCommon

–t(∅)

tPD,LINE(FB)

QFBDevice 1

Any QDevice 1

tJIT(∅)

+tSK(O)

QFBDevice2

+t(∅)

tJIT(∅)

Any QDevice 2

+tSK(O)

Max. skew

tSK(PP)

Figure 7. MPC961C max. device-to-device skew

Due to the statistical nature of I/O jitter a rms value (1 s) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 8.

MOTOROLA

For More Informa6tion On This Product,

Go to: www.freescale.com

TIMING SOLUTIONS

DL207 — Rev 0

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