MPC905
1:6 PCI Clock Generator/Fanout BuffFerreescale Semiconductor, Inc.
NETCOM
MPC905
shows a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The
parallel combination of the 40Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/55) = 1.36V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.73V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
OutA
2.5
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
0.5
0
2
4
6
8
10
12
14
TIME (nS)
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC905
OUTPUT
BUFFER
10Ω
RS = 30Ω ZO = 50Ω
RS = 30Ω ZO = 50Ω
10Ω + 30Ω k 30Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
IDT™ 1:6 PCI Clock Generator/Fanout Buffer
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MPC905
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