MPXY8020A6T1 データシートの表示（PDF） - Freescale Semiconductor

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MPXY8020A6T1

Tire Pressure Monitoring Sensor Temperature Compensated and Calibrated, Fully Integrated, Digital Output

Freescale Semiconductor 

OUT

RST

2/f LFO

2/f LFO

Standby

≈ 3 Sec

≈ 52 Minutes

Figure 4. Pulse on RST Pin

S0 Pin

The S0 pin is used to select the mode of operation as

shown in Table 1.

The S0 pin contains an internal Schmitt trigger as part of

its input to improve noise immunity. The S0 pin has an

internal pull-down device in order to provide a low level when

the pin is left unconnected.

S1 Pin

The S1 pin is used to select the mode of operation, as

shown in Table 1.

The S1 pin contains an internal Schmitt trigger as part of

its input to improve noise immunity. This pin has an internal

pull-down device to provide a low level when the pin is left

unconnected.

The S1 pin also serves the purpose of enabling factory trim

and test of the device.

The higher VPP programming voltage for the internal

EEPROM trim register is also supplied through the S1 pin.

DATA Pin

The DATA pin is the serial data in (SDI) function for setting

the threshold of the voltage comparator.

The DATA pin contains an internal Schmitt trigger as part

of its input to improve noise immunity. This pin has an internal

pull-down device to provide a low level when the pin is left

unconnected.

CLK Pin

The CLK pin is used to provide a clock used for loading

and shifting data into the DATA pin. The data on the DATA pin

is clocked into a shift register on the rising edge of the CLK

pin signal. The data is transferred to the D/A Register on the

eighth falling edge of the CLK pin. This protocol may be

handled by the SPI or SIOP serial I/O function found on some

MCU devices.

The CLK pin contains an internal Schmitt trigger as part of

its input to improve noise immunity. The CLK pin has an

internal pull-down device to provide a low level when the pin

is left unconnected.

Output Threshold Adjust

The state of the OUT pin is driven by a voltage comparator

whose output state depends on the level of the input voltage

on the sample capacitor and the level of an adjustable 8-bit

threshold voltage. The threshold is adjusted by shifting data

bits into the D/A Register (DAR) via the DATA pin while

clocking the CLK pin. The timing of this data is shown in

Figure 4. Data is transferred into the serial shift register on

the rising edge of the CLK pin. On the falling edge of the 8th

clock the data in the serial shift register is latched into the

parallel DAR register. The DAR remains powered up

whenever VDD is present. The serial data is clocked into the

DATA pin starting with the MSB first. This sequence of

threshold select bits is shown in Table 2.

Table 2. D/A Threshold Bit Assignment

Function

Voltage Comparator Threshold Adjust (8 bits)

LSB

MSB

Bit Weight

1

2

4

8

16

32

64

128

Data Bit

D0

D1

D2

D3

D4

D5

D6

D7

MPXY8000

4

Sensor Devices

Freescale Semiconductor

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