Table 6. Control Timing
+2.1 V ≤ VDD ≤ +3.6 V, TL ≤ TA ≤ TH, unless otherwise specified.
Characteristic
Symbol
HFO Measurement Clock Frequency
fHF
LFO Wake Up Clock Frequency
Ta = –40°C, +2.1V ≤ VDD ≤ +3.6
fLF
Ta = +25°C, +2.1V ≤ VDD ≤ +3.6
fLF
Ta = +125°C, +2.1V ≤ VDD ≤ +3.6
fLF
Wake Up Pulse
Pulse Timing
Pulse Width
Reset Pulse
Pulse Timing
Pulse Width
Minimum Setup Time (DATA edge to CLK rise)
tWAKE
tWPW
tRESET
tRPW
tSETUP
Minimum Hold Time (CLK rise to DATA change)
tHOLD
Measurement Response Time
Recommended time to hold device in measurement mode
Temperature
Pressure
Read Response Time (see Figure 8)
From 90% VDD on S0 to OUT less than VOL or greater than VOH
tTMEAS
tPMEAS
tREAD
Sample Capacitor Discharge Time
From initial full scale D/A count (255) to drop 2 counts (253)
tSH
Min
100
3300
3900
3800
Typ
135
5400
5400
5300
Max
150
8000
7700
7000
Units
kHz
Hz
Hz
Hz
—
16384
—
—
2
—
—
16,777,216
—
—
2
—
100
—
—
100
—
—
LFO clocks
LFO clocks
LFO clocks
LFO clocks
nSec
nSec
—
200
—
µSec
—
500
—
µSec
—
50
100
µSec
20
—
—
mSec
Test Point
50 pF
VDD
6.32 kΩ
10.91 kΩ
Figure 8. Control Timing Test Load for OUT and RST Pins
MPXY8000
8
Sensor Devices
Freescale Semiconductor