CXB1565R データシートの表示（PDF） - Sony Semiconductor

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CXB1565R

622Mbps Clock & Data Recovery with High Sensitivity Limitting Amplifier

Sony Semiconductor 

CXB1565R

Notes on Operation

1. Limiting amplifier block

The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and

C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and

IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external

capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since

peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on

the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target

values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is

used, provide AC grounding by connecting Pin 29 to a capacitor which has the same capacitance as capacitor

C1.

R1 (internal): 1.5kΩ

C1 (external): 470pF

f2: 225kHz

R2 (internal): 10kΩ

C2 (external): 0.022µF

f1: 723Hz

D

28

C1

29

C1

34

C2

35

R1

R1

R2

R2

Fig. 1

To IC interior

Feedback

frequency response

Amplifier

frequency response

f1 f2

Frequency

Fig. 2

– 11 –

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