MS81V04160A データシートの表示（PDF） - Oki Electric Industry

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MS81V04160A

Dual FIFO (262,214 Words × 8 Bits) × 2

Oki Electric Industry 

1Semiconductor

FEDS81V04160A-01

MS81V04160A

PIN DESCRIPTION

Data Inputs: (DIN10 to 17)

These pins are used for serial data inputs.

Write Reset: RSTW1

The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW1

setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely

controlled by the SWCK rising edge after the high level of RSTW1, the states of WE1 and IE1 are ignored in the

write reset cycle. Before RSTW1 may be brought high again for a further reset operation, it must be low for at least

two SWCK cycles.

Write Enable: WE1

WE1 is used for data write enable/disable control. WE1 high level enables the input, and WE1 low level disables

the input and holds the internal write address pointer. There are no WE1 disable time (low) and WE1 enable time

(high) restrictions, because the MS81V04160A is in fully static operation as long as the power is on. Note that

WE1 setup and hold times are referenced to the rising edge of SWCK.

Input Enable: IE1

IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The internal write address

pointer is always incremented by cycling SWCK regardless of the IE1 level. Note that IE1 setup and hold times are

referenced to the rising edge of SWCK.

Data Out: (DOUT0 to 11)

These pins are used for serial data outputs.

Read Reset: RSTR1

The first positive transition of SRCK after RSTR1 becomes high resets the read address pointers to zero. RSTR1

setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled

by the SRCK rising edge after the high level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle.

Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK

cycles.

Read Enable: RE1

The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When RE1 is high before the

rising edge of SRCK, the read pointer is incremented. When RE1 is low, the read pointer is not incremented. RE1

setup times (tRENS and tRDSS) and RE1 hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK

clock.

Output Enable: OE1

OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal read address pointer is

always incremented by cycling SRCK regardless of the OE1 level. Note that OE1 setup and hold times are

referenced to the rising edge of SRCK.

Serial Write: Clock SWCK

The SWCK latches the input data on chip when WE1,2 and IE1,2 are high, and also increments the internal write

address pointer when WE1,2 is high. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of

SWCK.

Serial Read Clock: SRCK

Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE1, 2 is high during a

read operation. The SRCK input increments the internal read address pointer when RE1, 2 is high.

The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same

polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of

SRCK.

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