MS81V04160A データシートの表示（PDF） - Oki Electric Industry

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MS81V04160A

Dual FIFO (262,214 Words × 8 Bits) × 2

Oki Electric Industry 

1Semiconductor

FEDS81V04160A-01

MS81V04160A

AC Characteristics Measuring Conditions

Output Compare Level

Output Load

Input Signal Level

Input Signal Rise/Fall Time

Input Signal Measuring Reference Level

1.5 V / 1.5 V

1 TTL + 30 pF

3.0 V / 0.0 V

3 ns

1.5 V

1. Input voltage levels for the AC characteristic measurement are VIH = 3.0 V and VIL= 0 V.

The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and

VIL = 0 V.

2. AC measurements assume tT = 3 ns.

3. Read address must have more than a 150 address delay than write address in every cycle when

asynchronous read/write is performed.

4. Read must have more than a 150 address delay than write in order to read the data written in a

current series of write cycles which has been started at last write reset cycle: this is called “new data

read”. When read has less than a 20 address delay than write, the read data are the data written in

a previous series of write cycles which had been written before at last write reset cycle: this is called

“old data read”.

5. When the read address delay is between more than 21 and less than 149 or more than 262,214, read

data will be undetermined. However, normal write is achieved in this address condition.

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