MSC1162 データシートの表示（PDF） - Oki Electric Industry

部品番号

コンポーネント説明

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MSC1162

40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver

Oki Electric Industry 

¡ Semiconductor

MSC1162A

PIN DESCRIPTION

Symbol

CLK

DIN

DOUT

LS

CL

CHG

VHO1-40

VHV

VCC

GND1

GND2

Type

I

I

O

I

I

I

O

Description

Shift register clock input pin.

Shift register reads data through DIN while the CLK pin is low state and the data in the shift

register is shifted from one stage to the next stage at the rising edge of the clock.

Serial data input pin of the shift register.

Display data (positive logic) is input in through the DIN pin synchronization with clock.

Serial data output pin of the shift register.

Data is output through the DOUT pin in synchronization with the CLK signal.

When R/L = High, the data of PO40 in the shift register is output through the DOUT pin.

When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin.

Latch strobe input pin

When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS

goes from high to low, the parallel output data (PO1-40) of the shift register is held.

Clear input pin with a built-in pull-up resistor

The CL pin is normally being set high.

If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase

with the corresponding latch outputs (O1 to O40).

If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high

irrespective of the states of the latch outputs.

If the CL pin is set low, the driver outputs are driven low irrespective of the states of the

CHG pin and latch outputs.

This allows display blanking to be set.

Input for testing (with a pull-down resistor)

The CL pin is normally being set low.

If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase

with the corresponding latch outputs (O1 to O40).

If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low

irrespective of the states of the latch outputs.

If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the

latch outputs.

This provides the easy testing of all lights after final assembly.

High voltage driver outputs for driving VFD tube

The driver outputs are in phase with the corresponding latch outputs (O1 to O40).

The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.

Power supply pin for driver circuits of VFD tube

Power supply pin for logic

GND pin for driver circuits of a VFD tube. (D-GND)

Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND.

GND pin for the logic circuits. (L-GND)

Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.

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