NJU6676CH データシートの表示（PDF） - Japan Radio Corporation

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NJU6676CH

64-Common X 132-Segment plus 1-Icon Bit Map Type LCD Controller and Driver

Japan Radio Corporation  

NJU6676

PRELIMINARY

Functional description

(1) Block circuits description

(1-1) Busy Flag (BF)

During internal operation, the LSI is being busy and can’t accept any instructions except “status

read”. The BF data is output through D7 terminal by the “status read” instruction.

When the cycle time (tcyc) mentioned in the “AC characteristics ” is satisfied, the BF check isn’t

required after each instruction, so that MPU processing performance can be improved.

(1-2) Initial display line register

The initial display line register assigns a DDRAM line address, which corresponds, to COM0 by

“initial display line set” instruction. It is used for not only normal display but also vertical display

scrolling and page switching without changing the contents of the DDRAM.

However, the 65th address for icon display can’t be assigned for initial display line address.

(1-3) Line counter

The line counter provides a DDRAM line address. It initializes its contents at the switching of frame

timing signal (FR), and also counts-up in synchronization with common timing signal.

(1-4) Column address counter

The column address counter is an 8-bit preset counter which provides a DDRAM column address,

and it is independent of below-mentioned page address register.

It will increment (+1) the column address whenever “display data read” or “display data write”

instructions are issued. However, the counter will be locked when no-existing address above (84)H

are addressed. The count-lock will be able to be released by the “column address set” instruction

again. The counter can invert the correspondence between the column address and segment driver

direction by means of “ADC set” instruction.

(1-5) Page address register

The page address register provides a DDRAM page address.

The last page address “8” should be used for icon display because the only D0 is valid.

(1-6) Display data RAM (DDRAM)

The DDRAM contains 8,580-bit, and stores display data which is 1-to-1 correspondents to LCD

panel pixels.

When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse

display mode, “1” turns off and “0” turns on.

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