1Semiconductor
FEDL9225B-03
MSM9225B
Symbol
Mode1, 0
Pin
29, 30
Type
Description
Microcontroller interface select pins
Mode1 Mode0
Interface
0
0 Parallel Separate No address latch signal
I
0
1 mode buses
With address latch signal
1
0
Multiplexed buses
1
1 Serial mode
INT
RESET
XT
XT
Rx0, Rx1
Tx0, Tx1
VDD
GND
Interrupt request output pin
When an interrupt request occurs, a “L” level is output. This pin
11
O automatically outputs a “H” level after 32 Ts (T = 1/fosc).
Three types of interrupts share this pin: transmission complete, reception
complete, and error.
Reset pin
25
I
System is reset when this pin is at a “L” level.
13
I Clock pins. If internal oscillator is used, connect a crystal (ceramic
resonator).
14
O If external clock is used, input clock via XT pin. The XT pin should be left
open.
18, 19
I Receive input pin. Differential amplifier included.
22, 23
O Transmission output pin
12, 20, 24, 40 — Power supply pin
6, 15, 17, 21, — GND pin
28, 39
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