M28LV64 データシートの表示（PDF） - STMicroelectronics

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M28LV64

64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION

STMicroelectronics 

M28LV64

Table 3. Operating Modes (1)

Mode

Standby

Output Disable

Write Disable

Read

Write

Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH.

E

G

W

1

X

X

X

1

X

X

X

1

0

0

1

0

1

0

DQ0 - DQ7

Hi-Z

Hi-Z

Hi-Z

Data Out

Data In

DESCRIPTION (cont’d)

The M28LV64 outputs the Ready/Busy write

status, the M28LV64-aaaX(aaa = access time) has

no Ready/Busy status and the relevant RB pin is

Not Connected (NC). The circuit has been de-

signed to offer a flexible microcontroller interface

featuring both hardware and software handshak-

ing with Ready/Busy, Data Polling and Toggle Bit.

The M28LV64 supports 64 byte page write opera-

tion. A Software Data Protection (SDP) is also

possible using the standard JEDEC algorithm.

PIN DESCRIPTION

Addresses (A0-A12). The address inputs select

an 8-bit memory location during a read or write

operation.

Chip Enable (E). The chip enable input must be

low to enable all read/write operations. When Chip

Enable is high, power consumption is reduced.

Output Enable (G). The Output Enable input con-

trols the data output buffers and is used to initiate

read operations.

Data In/ Out (DQ0 - DQ7). Data is written to or read

from the M28LV64 through the I/O pins.

Write Enable (W). The Write Enable input controls

the writing of data to the M28LV64.

Ready/Busy (RB). Ready/Busy is an open drain

output that can be used to detect the end of the

internal write cycle (this function applies only to the

M28LV64).

OPERATION

In order to prevent data corruption and inadvertent

write operationsan internal VCCcomparator inhibits

Write operation if VCC is below VWI (see Table 6).

Access to the memory in write mode is allowed after

a power-up as specified in Table 6.

Read

The M28LV64 is accessed like a static RAM. When

E and G are low with W high, the data addressed

is presented on the I/O pins. The I/O pins are high

impedance when either G or E is high.

Write

Write operations are initiated when both W and E

are low and G is high.The M28LV64 supports both

E and W controlled write cycles. The Address is

latched by the falling edge of E or W which ever

occurs last and the Data on the rising edge of E or

W which ever occurs first. Once initiated the write

operation is internally timed until completion.

Page Write

Page write allows up to 64 bytes to be consecu-

tively latched into the memory prior to initiating a

programming cycle. All bytes must be located in a

single page address, that is A6-A12 must be the

same for all bytes. The page write can be initiated

during any byte write operation.

Following the first byte write instruction the host

may send another address and data with a mini-

mum data transfer rate of tWHWH (see Figure 13).

If a transition of E or W is not detected within tWHWH

the internal programming cycle will start.

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